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The Senior Hardware Engineer will drive product development from concept to production, create hardware specs, and ensure system validation. They will collaborate with cross-functional teams and address technical challenges in embedded computing system design.

Lead the design and development of UEFI firmware for server platforms, focusing on Host-to-BMC communication and integration of security features.

The ASIC Design Engineer will develop SoCs, micro-architecture design, RTL coding, optimization, and collaborate with multiple teams for ASIC development.

Lead integration of security solutions with NVIDIA systems, focusing on debugging, protocol development, and BMC firmware optimization to ensure compliance and system reliability.

Responsible for designing, developing, and maintaining BMC software solutions, ensuring high-quality code through reviews and debugging, and documenting specifications. Requires expertise in various communication protocols and firmware implementation.

Design, develop, and maintain BMC software solutions, implementing firmware communication, performing code reviews, and preparing documentation.

The Staff FPGA Engineer will validate high-speed communication protocols, implement FPGA logic, integrate designs into CI/CD environments, and debug hardware issues.

The ASIC Design Engineer will design and implement SoCs, optimize performance, collaborate with teams, and support chip validation through the design flow.

Lead the design, development, and optimization of secure firmware solutions, focusing on Platform Firmware Resiliency and compliance with security standards. Collaborate with cross-functional teams and mentor engineers in firmware security principles.

The BMC Engineer designs, develops, and maintains BMC software, focusing on firmware communication with peripherals, performing code reviews, unit testing, and documentation.