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The Senior Emulation Design Engineer will convert complex SOC designs into emulation environments, validate interoperability with AI servers, and optimize performance. Responsibilities include debugging, integrating IPs, and collaborating with multiple teams.

The Senior FPGA Design Engineer will engage in RTL design, FPGA simulation, system validation, and debug, collaborating with several teams in a fast-paced environment.

The Silicon Test Engineer at Axiado will develop, debug, and optimize ATE and SLT test programs while collaborating with cross-functional teams to ensure comprehensive test coverage for silicon validation and production.

The Staff ASIC Design Engineer will lead ASIC design projects, implement micro-architecture optimizations, and collaborate across teams to develop silicon products.

The ASIC Design Engineer will develop SoCs, optimize performance and power, collaborate with various teams, and support testing and validation processes.

Lead product definition and roadmap for the Trusted Control/Compute Unit (TCU) platform across software, firmware, and on-chip AI/ML. Define PRDs and acceptance criteria, drive cross-functional alignment with hardware and engineering, engage hyperscaler and OEM customers on integration, influence standards, support launches, and grow the PM function.

The NPI Engineer will manage the transition of new products from design to manufacturing, collaborate with teams, analyze data, and improve processes.

Responsible for designing, developing, and maintaining BMC software solutions. Engage in firmware communication, code reviews, and ensure high-quality software through testing and debugging.

Develop and implement SoCs, focusing on micro-architecture design, RTL coding, synthesis, and timing closure, while collaborating with various teams throughout ASIC development.

Design, develop, and integrate BMC software solutions for system management. Collaborate with customers on technical issues and ensure compliance with security protocols.