Top Tech Jobs & Startup Jobs

Lead foundry-facing technical activities to enable process adoption and on-time tape-out. Manage PDK readiness, align design/signoff flows with foundry requirements, define device test structures, support silicon characterization, and scale technology collateral and methodology across teams.

Lead development of connectivity IP for Lattice FPGAs, translating specifications into high-speed RTL designs. Perform RTL design, logic verification, debug, timing closure, and collaborate on validation, soft IP packaging, example designs, and testbenches while mentoring and enabling engineering teams.

Design and implement custom and digital semiconductor designs. Develop RTL in Verilog/SystemVerilog, perform transistor-level and schematic work, run simulations and timing/DFT flows, script automation, and support product development and tapeout activities.

Lead cross-functional FPGA silicon, Soft-IP and software tool programs. Manage scope, schedule, risks, resources, and stakeholder alignment across global teams to ensure timely, high-quality product delivery and executive reporting.

Design and develop analog/mixed-signal IC blocks from specification through post-silicon verification. Perform circuit design and simulation, collaborate on physical layout, integrate analog blocks into digital chips, define bench test plans, perform post-silicon characterization and debug, and mentor junior engineers.

Design, develop, and maintain FPGA software tools and infrastructure; implement features for next-generation FPGA products; support existing tools; produce functional specifications and unit test plans; review marketing requirements; improve development methodologies and collaborate across teams.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Maintain and optimize custom layout CAD flows using Cadence Virtuoso and related EDA tools. Develop automation (SKILL, Python, Tcl, Perl) for handoffs, PDK enablement, libraries, and CI pipelines. Debug tool/flow issues, evaluate EDA quality, collaborate with design and foundry teams, mentor engineers, and support global CAD infrastructure including version control and compute farm tools.

Develop and improve FPGA place-and-route software tools focusing on Isolation Design Flow and QoR (performance, area, runtime, memory). Implement new features, support new FPGA products, write unit tests, collaborate cross-functionally, and support customer needs.

Lead design and optimization of FPGA synthesis engines and toolchains. Drive QoR improvements (Fmax, area, compile time), define architecture and algorithms, modernize codebase, troubleshoot complex synthesis issues, and mentor engineers while aligning features to product roadmap.