Top Tech Jobs & Startup Jobs

Lead and support SEC financial reporting, US GAAP technical accounting, monthly/quarterly/annual close, SOX compliance, and operational accounting. Manage audits, mentor accounting staff, drive process and ERP improvements, and partner cross-functionally on acquisitions, stock-based compensation, and other complex transactions for a Nasdaq-listed semiconductor company.

Design and develop connectivity soft IP for Lattice FPGAs. Translate specifications into high-speed RTL focusing on performance, power and logic utilization. Collaborate with architects, implement RTL, perform verification, debug, timing closure, soft IP packaging, testbench development, and participate in hardware validation and interoperability testing.

Develop constrained-random testbenches and test plans from design specs, implement and execute tests, debug issues, analyze and collate results to closure, and document findings.

Support silicon product enablement for FPGA devices: drive feature enablement, create enablement collateral, provide factory and customer support, run trainings, resolve technical issues, and collaborate with sales and R&D to solidify requirements.

Manage material requirements, monitor WIP and safety stock to prevent production line-downs, coordinate with subcontractors on shipments and lead times, resolve inventory and delivery discrepancies, and collaborate with product planners to optimize inventory.

Design and ship LLM-powered agents to automate code generation, testing, review, and deployment. Collaborate with DevOps, QA, and ML teams to build AI-assisted development toolchains and integrate into CI/CD workflows.

Perform consolidated accounting for Lattice sales offices: month-end close journal entries, account reconciliations, financial review and analysis, SOX compliance and documentation, coordinate external audits, manage local statutory compliance, liaise with third-party accounting and payroll, process Concur reimbursements, and handle ad-hoc accounting tasks. Requires right to work in the Philippines and successful background/reference checks.

Develop and execute Pre-Si and Post-Si test plans for chip IP using FPGA-based test circuits and Lattice design tools. Automate test generation, run ATE and bench validations across process/temperature/voltage, perform root-cause analysis, drive IP content to closure, deliver test content on schedule, and extract coverage metrics using fault grading.

Lead design and development of Lattice FPGA software tools in Penang, focusing on FPGA primitives, Foundation IP and IP catalog tooling. Own release cycle planning, requirement analysis, feature scoping, development, testing and validation. Provide technical leadership, mentor engineers, and ensure delivery quality. Hands-on RTL, testbench, verification, timing closure, device modeling and EDA tool development using C++ and Python.

Lead foundry-facing technical activities to enable process adoption and on-time tape-out. Manage PDK readiness, align design/signoff flows with foundry requirements, define device test structures, support silicon characterization, and scale technology collateral and methodology across teams.