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Develop and maintain high-performance C++ functional models of Arm interconnect IP for system-level simulation. Collaborate with architects, hardware and CE-SW engineers to deliver incremental models, integrate software on virtual platforms, debug system-level issues, and improve modeling workflows. Communicate technical decisions and adapt to evolving specifications.

The Director of Segment Marketing will drive strategy for cloud infrastructure and financial markets, advocate for customers, build partnerships, and elevate marketing efforts to advance Arm's leadership in data center computing.

The role involves leading strategic sales for Arm within Financial Services and Cloud Infrastructure, driving relationships, opportunities, and adoption of Arm-based technologies across major institutions.

The role is accountable for strategic security leadership across semiconductor engineering environments, guiding teams in security practices while ensuring business efficiency.

Manage full lifecycle recruiting for interns and graduates, partner with hiring managers, maintain ATS data and hiring metrics, support campus events logistics, and ensure inclusive candidate experience.

Optimize production AI inference on Arm-based edge devices by developing kernel-to-system level implementations, profiling and resolving performance bottlenecks, producing production-quality reference code and documentation, and collaborating with customers and internal teams to influence IP and tooling roadmaps.

Lead and build a customer-facing engineering team to support SoC-based product integration from prototype to volume production. Act as technical liaison, resolve system-level hardware/software/manufacturing issues, report to senior management, mentor team members, and influence product roadmap using customer insights.

Define and evaluate next-generation CPU microarchitectures for Cortex-X and Neoverse, develop performance models and simulations, analyze workloads, estimate performance/power/area trade-offs, collaborate with design teams and partners, and mentor junior engineers.

Design and define high-speed on-chip interconnect architectures (coherent and non-coherent) including PCIe, CXL, and UA Link for scalable SoCs. Lead roadmap and early customer architecture engagements, collaborate with performance, power, physical design, software and firmware teams, and perform workload analysis and performance modeling to meet compute, memory, and interconnect targets.

The engineer will verify PCIe and CXL subsystems, collaborate on testplans, develop UVM testbenches, and improve verification methodologies.