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Design and define SoC security architectures including Root of Trust, Secure Boot, Key Management, Confidential Compute, attestation, secure manufacturing, and device lifecycle. Perform threat modeling, cryptographic analysis, hardware/software threat assessment, and collaborate across teams to develop security policies, access control, and mitigation strategies for hardware and firmware threats.

Lead global indirect tax compliance and strategy across sales/VAT, import duties, and non-income business taxes. Advise on transactions, contracts, audits, and supply-chain planning; manage tax audits and risk; oversee tax systems configuration and process automation; collaborate with finance, legal, procurement and operations; hire and develop a tax team and work on trade and customs matters.

Design and implement scalable platform services, runtimes, and developer tooling for deploying and managing AI workloads on Arm-based edge devices. Build abstractions, observability, and performance optimizations across heterogeneous hardware while collaborating with architects and AI engineers to produce robust, maintainable systems and SDKs for on-device AI.

Senior PCIe Verification Engineer responsible for creating and executing verification plans and testbenches for PCIe IP/SoC, debugging designs, collaborating with RTL designers and validation teams, and ensuring protocol compliance and quality.

Design and integrate PCIe, CXL, UCIe and other I/O subsystems into SoCs. Write micro-architecture specs, develop RTL in Verilog, run static checks, debug builds, collaborate with verification, performance, and backend teams, and mentor others to deliver complex SoC projects.

Design and integrate PCIe, CXL and other subsystems for SoCs: write micro-architecture specs, develop RTL in Verilog, debug, run static checks, collaborate with verification, performance analysis and backend teams, and mentor team members.

Lead workload and silicon-level performance analysis for next-generation server platforms (AI at scale and HPC). Define metrics and benchmarks, build microbenchmarks, identify bottlenecks, recommend architectural optimizations, and collaborate with hardware and software teams to validate improvements end-to-end.

The Principal High-Speed I/O Architect designs interconnect architectures for SoCs, collaborating on performance and efficiency in various markets.