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Develop embedded firmware and drivers for NCS products using Embedded C and RTOS. Work with microcontrollers and low-level interfaces (SPI, I2C, UART), toolchains (MPLAB), version control, and debugging tools through the full product lifecycle. Collaborate with teams and communicate effectively while performing independent development and troubleshooting.

Lead digital verification for next-generation microcontrollers and wireless SoCs. Build IP- and SoC-level UVM and formal verification environments, develop C testcases, integrate AI/ML-driven EDA tools and scripting, collaborate with global teams, and ensure RTL/ARM/RISC design correctness and timely delivery.

Design, simulate, and validate analog and mixed-signal IC blocks for SoCs, including PLLs, ADCs/DACs, high-speed I/Os and MEMS drivers. Develop behavioral models for mixed-signal simulations and perform block-level silicon validation and system-level lab evaluation.

The Technical Staff Engineer will design and develop analog ICs for Ethernet and USB products, collaborate with cross-functional teams, and ensure high-quality standards. Responsibilities include creating specifications, performing simulations, and meeting aggressive timelines for product development.

The Senior Manager - Product Marketing will drive business development strategy for Mixed-Signal products, translating customer insights into product positioning while collaborating with internal teams to boost revenue and design wins worldwide.

Lead Zephyr RTOS architecture and enablement across Microchip products. Define roadmap, drive platform and open-source integration, coordinate cross-functional teams, mentor engineers, support customer and partner adoption, and represent Microchip in the Zephyr community.

Design, simulate and validate analog and mixed-signal IC blocks (PLLs, ADCs/DACs, filters, high-speed I/Os). Develop behavioral models (Verilog-A) for top-level simulation, perform process-corner simulations, automate flows with scripting, and validate silicon and system-level lab performance while collaborating with analog leads and multi-site teams.

Lead design and implementation of secure embedded controller and cryptographic ICs. Drive architecture, RTL development, verification, and bring-up. Support integration activities (lint, CDC, synthesis, DFT), work with physical design on STA/power/floorplanning, debug hardware/firmware interactions, and collaborate across global teams to deliver automotive, industrial, and security-focused ASIC/FPGA products.

Lead IO and pad ring planning for advanced SoC storage and memory controller designs. Create and validate pad ring DEFs, bump maps, IO netlists, and handoff deliverables. Coordinate with architecture, IP, packaging, implementation, foundry, and verification teams to ensure IO/package compliance, support silicon debug, and drive design improvements.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.