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Provide technical support and enablement for Ethernet PHY and switch products: answer customer and field questions, create application collateral and example code, identify gaps in enablement, define high-level requirements for development, and deliver technical training and workshops to customers and sales/field engineers.

The role involves defining Mixed-Signal IP requirements, collaborating with vendors, managing IP processes, and supporting lab testing for analog and mixed-signal circuits.

Lead physical design tasks for 32-bit mixed-signal and wireless microcontroller products: floorplanning, placement, CTS, routing, timing closure, low-power and multi-voltage island design, physical verification, automation/flow development, die sizing, vendor/IP interfacing, and cross-team collaboration.

The role involves developing methodologies for signal and power integrity in high-speed FPGA products, collaborating with global teams, and providing technical guidance on SI/PI strategies.

Design, develop, integrate, simulate, and validate analog circuit blocks and Flash-IP macros for analog compute-in-memory and embedded flash applications. Lead architecture definition, circuit implementation, silicon validation, debugging, and testing. Collaborate with design, technology, process, testing, marketing, and customer teams to deliver reliable products and address technical requirements.

Perform block- and full-chip DFT for ASIC/SoC designs including boundary-scan, memory BIST, scan insertion with compression, ATPG and pattern verification, gate-level simulation, silicon bring-up and failure debug on ATE, and collaborate with RTL/STA teams to resolve timing and DFT DRC issues.

Lead systems engineering for timing, position, and RF communications products: define requirements, design embedded systems and algorithms, implement and validate solutions, collaborate with hardware/software/FPGA/mechanical teams, coordinate product release with manufacturing/quality, and support system integration and customer installations. Travel up to 15%.

Lead DFT architect responsible for improving test architecture and coverage across SoC designs. Implement and run Tessent/Modus ATPG and MBIST flows, perform scan pattern simulation, diagnosis and post-silicon bring-up, and collaborate with test engineering for pattern delivery and debug.

Design and verify digital ASIC blocks for multi-gigabit Ethernet PHYs: develop RTL, run functional verification and bit-matching, perform pre-silicon FPGA emulation, support silicon bring-up, and mentor junior engineers while collaborating across analog, firmware, and validation teams.

Provide technical leadership for high-power solutions: support customers and sales, drive design wins, define system-level solutions, develop application content, mentor engineers, and support product and market strategy across power semiconductor technologies.