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The Staff Capacity Planner will collaborate with various teams to analyze demand signals, manage supply constraints, enhance planning processes, and drive capacity investment opportunities.

The role involves designing and verifying protection and small signal products, collaborating with cross-functional teams, and ensuring manufacturing quality.

The role involves designing secure AI architectures, collaborating with teams, guiding architectural decisions, and improving governance processes in cybersecurity contexts.

Perform accounts payable tasks including manual three-way invoice matching, vendor reconciliations, monthly AP close (accruals, cut-off checks, aging), SOX/audit support, AP clean-up projects, and support for AP shared services.

Lead the global Travel & Expense program, driving strategic sourcing, supplier management, governance, reporting, compliance, automation, and a multi-year T&E transformation. Own RFIs/RFPs, supplier scorecards, program roadmap, cross-functional stakeholder alignment, reporting/dashboard development, and AI-enabled process improvements to improve compliance, traveler experience, cost visibility, and supplier performance.

Lead architecture, design, and verification of mixed-signal digital IP (e.g., ADCs, DACs, PLLs) for automotive, industrial, and medical SoCs. Drive CMOS/SOI designs and reusable IP, lead small teams, contribute to SoC integration, DFT strategies, and documentation. Collaborate with test, product, and applications engineering to ensure production release and propose innovative technical solutions.

Perform electrical characterization and statistical analysis for trench MOSFETs, IGBTs, and power semiconductor devices. Investigate production issues, evaluate process changes, support qualification and technology transfers, correlate test and reliability data, recommend dispositions, and drive automated data-analysis methods to improve yield and manufacturing continuity.

Lead architecture, design, and verification of mixed-signal and digital IP (DAC/ADC/PLL, wireless interfaces). Drive CMOS/SOI designs, lead small teams, support SoC integration, DFT strategies, documentation, and partner with test/product teams for production release.

Perform accounts payable tasks including three-way invoice matching, vendor query resolution, monthly AP close activities, accruals and aging review, SOX/audit support, and AP cleanup projects while supporting AP shared services.

Design and advise on secure, scalable AI-enabled architectures; co-lead solution design with cross-functional teams; evaluate risks and prepare architecture assessments for an AI Architecture Technical Committee; develop governance, guardrails, templates, and reusable patterns; mentor architects and engineers; and integrate AI safely into security tooling (SIEM, SOAR, EDR/XDR) to improve automation and threat detection.