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25 Days AgoSaved
In-Office
Palo Alto, CA, USA
175K-280K Annually
Senior level
175K-280K Annually
Senior level
Aerospace • Other
Lead digital ASIC verification at block and system levels: author and execute test plans, develop test harnesses and regressions, drive coverage closure, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex designs.
Top Skills: AsicCode CoverageConstrained-Random VerificationFunctional CoverageOvmPythonRtlTestbenchUvmVmm
25 Days AgoSaved
In-Office
Hawthorne, CA, USA
105K-150K Annually
Junior
105K-150K Annually
Junior
Aerospace • Other
Design and implement RF and analog IC layouts for advanced-node silicon, collaborate on floorplanning, power/ground distribution and packaging, run DRC/ERC/LVS and manufacturability checks, integrate top-level layout and ESD/pad assemblies, and support EDA tool trials and team training.
Top Skills: CadenceEda ToolsGdsiiLinuxPerlPythonRevision Control SystemsShell ScriptingSkill
25 Days AgoSaved
In-Office
Bastrop, TX, USA
Junior
Junior
Aerospace • Other
Lead a team to ensure Starlink hardware reliability from factory to field: define strategy, run root-cause investigations, develop reliability qualification and testing, automate test/data analysis, drive production quality and process improvements, monitor field metrics, and mentor engineers while ensuring ISO/quality compliance.
Top Skills: As9100Data VisualizationEnvironmental TestingIso 9001Log AnalysisPcbPcbaPhased-ArrayReliability TestingRfTelemetryTest AutomationWi-Fi Standards
25 Days AgoSaved
In-Office
Palo Alto, CA, USA
135K-210K Annually
Junior
135K-210K Annually
Junior
Aerospace • Other
Develop and execute digital ASIC verification at block and system levels. Create SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon, chip bring-up and post-silicon validation.
Top Skills: AsicDspMatlabPythonRtlSystemverilogUvm
25 Days AgoSaved
In-Office
Redmond, WA, USA
125K-175K Annually
Junior
125K-175K Annually
Junior
Aerospace • Other
Support and improve EDA/IC design environments for RFIC and silicon teams: triage tool/PDK/HPC issues, maintain wrappers and runbooks, build lightweight automation and QA tests, manage PDK deployments, and partner with design, foundry, IT, and vendors to improve reproducibility and methodology.
Top Skills: Cadence Ade AssemblerCadence Ade ExplorerCadence PegasusCadence VirtuosoCliosoftEmxFlexnetHfssHpcKeysight AdsLinuxLsfMakefileNfsPdkPerforcePerlPythonQuantusShellSiemens CalibreSkillSlurmSpectreStarrcSynopsys Digital ToolsSynopsys IcvTcl
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25 Days AgoSaved
In-Office
Irvine, CA, USA
125K-195K Annually
Junior
125K-195K Annually
Junior
Aerospace • Other
Develop and execute digital ASIC verification at block and system levels. Build SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification, chip bring-up, and post-silicon validation.
Top Skills: AsicConstrained Random VerificationDspMatlabPythonRtlSystemverilogUvm
25 Days AgoSaved
In-Office
Redmond, WA, USA
125K-195K Annually
Junior
125K-195K Annually
Junior
Aerospace • Other
Verify digital ASICs at block and system level: write and execute test plans, build SystemVerilog (UVM and non-UVM) testbenches, run regressions and close coverage, automate tests with Python/MATLAB, and support pre-silicon verification, chip bring-up and post-silicon validation.
Top Skills: AsicConstrained-Random VerificationDspMatlabPythonRtlSystemverilogUvm
25 Days AgoSaved
In-Office
Austin, TX, USA
Junior
Junior
Aerospace • Other
Develop and execute digital ASIC verification at block and system level. Build SystemVerilog (UVM and non-UVM) testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification through post-silicon validation and chip bring-up.
Top Skills: AsicDspMatlabPythonRtlSystemverilogUvm
25 Days AgoSaved
In-Office
Irvine, CA, USA
125K-175K Annually
Junior
125K-175K Annually
Junior
Aerospace • Other
Support and improve EDA/CAD workflows for RFIC and silicon teams by triaging tool/PDK issues, maintaining tool wrappers and runbooks, building lightweight automation and QA tests, partnering with vendors and foundries, and converting recurring support items into durable flow improvements.
Top Skills: Ansys Hfss/EmxCadence Ade Explorer/AssemblerCadence PegasusCadence QuantusCadence VirtuosoCliosoftFlexnetKeysight AdsLinuxLsfMakefileNfsPdksPerforcePerlPythonShellSiemens CalibreSkillSlurmSpectreSynopsys IcvSynopsys StarrcTcl
25 Days AgoSaved
In-Office
Star, TX, USA
Junior
Junior
Aerospace • Other
Design, install, and support fiber and copper network cabling, voice, video, RF, ground stations, telemetry and optical tracking systems. Troubleshoot electrical and telecom equipment, coordinate downtime and procurement, manage construction contracts, support field technicians, and oversee installations to meet standards and mission requirements.
Top Skills: Ansi/TiaAutocadAutomatic Transfer SwitchesBackup GeneratorsBicsi RcddCopper CablingFiberopticGround StationsInternational Building Code (Ibc)Isp/Osp Structured CablingLanLteMarine CommunicationsNational Electric Code (Nec)National Fire Protection Association (Nfpa)Optical Tracking SystemsRevitRf SystemsTelemetry SystemsUps SystemsWanWifi
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