Top Tech Jobs & Startup Jobs

Perform SoC physical design: block-level floorplanning, partitioning, placement, CTS, routing, and physical verification (LVS/DRC/ERC/antenna). Drive timing closure, congestion resolution, STA, crosstalk/noise analysis, power optimization, equivalence checks, formal verification, and timing/functional ECO implementation. Mentor team members and collaborate in a global, dynamic environment.

Perform SOC physical design including block-level floorplanning, partitioning, placement, CTS, routing and physical verification (LVS/DRC/ERC/Antenna). Drive STA, equivalence checks, crosstalk/noise analysis, power optimization and implement timing/functional ECOs. Mentor team members, work in global teams, and use/learn EDA tools for timing closure and congestion resolution.

Senior Digital VLSI Design Engineer responsible for defining and enforcing multi-clock synchronization, creating synthesis constraints, and driving full-chip CDC/RDC and DFT sign-off. Collaborate with architecture and chip leads to identify metastability and reset issues pre-RTL freeze, mentor teams, and implement automated sign-off flows for complex high-speed IPs.

As a Principal Hardware Engineer, you will design and deliver electronic products, lead technical teams, and oversee comprehensive EE hardware design.

Integrate and maintain commercial AI tools and LLM agents into VLSI design flows, coordinate multi-agent systems, optimize performance and QoR, deploy AI agents and chatbots, preprocess data, evaluate solutions, and train end-users to improve design productivity.

Implement physical design tasks including floorplanning, placement, design closure, STA, DRC/LVS and full-chip signoff (PI, SI, PV). Independently handle block and top-level implementation, support tapeout at 7nm and below, and use scripting (Perl/Tcl). Strong problem solving and communication skills required; DFT, power/IVD, and verification experience are a plus.

Perform SoC physical design across block-level floorplanning, partitioning, placement, CTS, routing and physical verification (LVS/DRC/ERC). Drive timing closure, congestion resolution, STA, crosstalk/noise analysis, power optimization, equivalence checks, formal verification and implement timing/functional ECOs using industry EDA tools.

Perform SoC physical design tasks including block-level floorplanning, partitioning, placement, CTS, routing, and physical verification (LVS/DRC/ERC). Achieve congestion, timing, and area targets; run equivalence checks, STA, crosstalk/noise analysis, power optimization, and implement timing/functional ECOs. Mentor teammates, work in global teams, and use/learn EDA tools.

Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below). Perform PPA optimization, CDC/RDC analysis, low-power design, timing closure, and hand off to physical design. Collaborate with Architecture, Verification, and Physical Design teams and drive SoC integration for high-speed memory and SerDes protocols.

Lead transformation from manual wafer start planning to system-driven demand and capacity planning for semiconductor fabs. Build wafer start plans, capacity models, and analytics; optimize throughput, identify bottlenecks, run scenario analyses, create dashboards/KPIs, and align cross-functionally with operations, engineering, supply chain, and finance.