Design, implement, verify, and optimize ultra-low-latency FPGA logic and reusable HDL building blocks. Own RTL development (VHDL/Verilog), timing closure, simulation, synthesis, board bring-up, hardware validation, and test automation using Python/Linux. Implement networking and system protocols (TCP/UDP, Ethernet MAC/PCS, PCIe, DMA). Mentor engineers, perform design reviews, and collaborate with architects, software, and product teams to deliver maintainable, high-performance FPGA solutions.

The Senior Network Engineer will support Exegy's network infrastructure, including administration, device maintenance, and collaboration with vendors for troubleshooting and changes.