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Lead technical strategy in 3D NAND thin film development, mentor engineers, influence standards, and drive process improvements.

As a Senior Data Scientist, you'll develop AI-driven solutions for manufacturing optimization, engage in data analytics, and enhance decision-making across departments.

Lead photolithography (PHOTO) process development and yield improvement for HBM and advanced packaging (2.5D/3D/chip stacking). Troubleshoot complex process issues, perform root-cause analysis, coordinate global materials and mechanical characterization/testing, advise on on-site project execution, and prepare technical reports and presentations. Collaborate with suppliers and cross-functional teams to meet specifications and roadmaps.

Provide senior architectural leadership for DRAM-related ASIC and logic solutions, driving high-bandwidth, energy-efficient, scalable, and reliable memory architectures. Lead silicon-package-system co-optimization, partitioning, interface definition, PPA and IO timing analysis, and practices to ensure first-silicon success. Mentor teams and influence cross-functional decisions to meet product and market requirements.

This role involves advancing thin film process development for NAND technology through experiments, material characterization, collaboration with teams, and project leadership.

Lead and develop a Procure-to-Pay operations team delivering global P2P support (tail spend, PR/PO processing, supplier onboarding, catalog, receiving, invoice resolution). Own service delivery KPIs, compliance, audit readiness, process documentation, stakeholder escalations, and continuous improvement. Act as P2P SME, drive automation/AI enablement, support system changes and UAT, and partner cross-functionally with Finance, IT, procurement, and suppliers.

The Process Engineer will develop and optimize processes for product quality and yield, coordinate evaluations, and support audits while resolving manufacturing issues.

The Facilities Engineer is responsible for overseeing UPW and WW systems operations, maintenance, and engineering projects, ensuring compliance and sustainability goals are met.

Lead custom analog and mixed-signal layout for LPDDR PHY blocks (datapath, IO, bias, references), drive high-speed interface layout, layout-aware co-design, power/ground/isolation strategies, physical verification and signoff (DRC/LVS/parasitics), post-layout optimization/ECOs, PPA improvements, mentoring, and automation using SKILL/Python/TCL and AI/ML to ensure first-pass silicon success and manufacturability.

Develop and execute OPC job decks and recipes for tapeouts, troubleshoot OPC process issues, automate verification and workflows, collaborate with cross-functional global teams, and communicate technical findings to improve yield, cycle time, and production stability.