Top Tech Jobs & Startup Jobs

Administer and improve enterprise infrastructure across Linux, Windows, macOS, cloud, virtualization, networking, storage, backup, identity, and endpoints. Develop automation, maintain secure configurations, monitor systems, remediate vulnerabilities, investigate incidents, and support compliance initiatives. Provide Tier 2/3 desktop engineering, device provisioning, onboarding and offboarding, endpoint management, troubleshooting, and documentation. Collaborate with engineering, security, and operations teams to deliver reliable, scalable, and secure infrastructure.

Lead RTL development for a next-generation Physical AI SoC, translating system architectures into production-quality microarchitectures and silicon. Responsibilities include hardware/software co-design, compute and memory subsystem design, interconnect and control logic, performance-power-area optimization, architecture and RTL reviews, cross-functional collaboration, process development, and mentoring RTL engineers. The role requires deep digital design expertise, Verilog/SystemVerilog experience, complex SoC development, and full-cycle ownership through silicon bring-up.

Own the functional safety architecture and lifecycle for Physical AI SoCs, from early architecture through tape-out, qualification, and production. Lead hazard analysis, FMEDA, FTA, fault analysis, safety metrics, and safety mechanisms across compute, AI accelerators, memory, and interconnects. Define hardware/software safety requirements, safety cases, and SEooC assumptions; coordinate certification and audits; establish safety processes; and mentor cross-functional silicon, firmware, software, and product teams.

Own the power architecture for Physical AI SoCs, including power domains, DVFS, power states, power delivery, and low-power techniques. Define on-die power management, PMIC interfaces, sensors, telemetry, and hardware/software controls. Establish energy and thermal budgets, model PPA trade-offs, integrate UPF-based power intent, and validate designs through silicon bring-up. Partner across silicon, firmware, thermal, package, and software teams while setting methodology standards and mentoring engineers.

Designs and evaluates AI model architectures for efficient hardware implementation. The role analyzes transformers and other models, translates computation graphs into hardware dataflows, develops performance and efficiency models, and collaborates across machine learning, software, and hardware teams. Responsibilities include optimizing models for specialized platforms and identifying opportunities for hardware-software co-design in cloud, edge, robotics, autonomous systems, and Physical AI.

Design and implement SoC power-management hardware, including digital power meters, activity monitors, throttlers, thermal control loops, clock and reset architecture, DVFS, power domains, retention, and low-power flows. Correlate power estimates across RTL, emulation, and silicon, and develop telemetry for power and thermal behavior. Collaborate with architecture, physical design, package, firmware, software, and verification teams.

Own and scale emulation infrastructure for a next-generation Physical AI SoC. Responsibilities include emulator bring-up, flow optimization, regression automation, HW/SW co-verification, pre-silicon software validation, waveform debugging, performance analysis, and FPGA prototyping. The role partners across architecture, RTL, verification, software, and systems teams to validate complex SoC designs and real-world workloads.

Leads RTL-to-gate synthesis, static timing analysis, timing closure, power optimization, and sign-off for advanced AI, CPU, VPU, and HPC silicon. Owns constraints, multi-mode multi-corner analysis, ECOs, low-power implementation, hierarchical timing convergence, and physical-aware optimization. Develops automation and implementation methodologies using Tcl, Perl, and Python while collaborating with RTL, DFT, physical design, CAD, verification, and product teams.

Leads financial strategy, planning, budgeting, forecasting, accounting operations, reporting, audits, tax compliance, cash flow, treasury, and capital allocation. Oversees a small finance team, improves financial systems and processes, supports growth initiatives and potential M&A, and provides financial insights to company leadership. Requires extensive high-tech startup finance experience and strong knowledge of GAAP, technical accounting, and financial modeling.

Owns end-to-end execution of a semiconductor SoC program from architecture through tapeout, silicon bring-up, and production readiness. Coordinates silicon, hardware, software, third-party IP vendors, foundries, OSATs, and manufacturing partners. Maintains integrated schedules, manages risks and dependencies, leads milestone reviews and executive reporting, drives decisions, and establishes program management processes for a growing engineering organization.