Top Tech Jobs & Startup Jobs

Own block-level and full-chip physical verification signoff for advanced ASIC and SoC designs through tape-out. Execute and debug DRC, LVS, ERC, PERC, antenna, reliability, density, and pattern-matching checks using Calibre and ICV. Drive physical ECOs in Innovus or Fusion Compiler, develop Tcl and scripting automation, resolve advanced-node issues, and collaborate across design, CAD, reliability, foundry, and EDA teams. Mentor engineers and optimize scalable signoff methodologies.

Design and optimize RTL for key portions of a high-performance, power-efficient SoC. Collaborate with architects, software, verification, and physical design teams on microarchitecture, hardware/software interfaces, memory systems, interconnects, compute engines, DMA, and power-management logic. Analyze performance, power, and area tradeoffs, resolve bottlenecks, and contribute to production silicon development for Physical AI applications.

Lead architecture, transistor-level design, optimization, and verification of high-performance, low-power standard cells and custom digital circuits for advanced AI and HPC silicon. Own PPA optimization, arithmetic circuit development, statistical and reliability verification, layout collaboration, characterization, ASIC sign-off, methodology improvements, and silicon readiness. Mentor engineers and provide technical leadership across circuit design and advanced semiconductor development.

Own and scale formal verification for complex SoC blocks, including CPUs, floating-point units, vector engines, and datapaths. Develop SVA properties, formal testbenches, constraints, abstractions, equivalence checks, and coverage strategies. Debug counterexamples, close difficult proofs, and build reusable formal applications. Partner with architecture, RTL, and simulation teams while maintaining automation, CI, regressions, and proof tracking. Apply formal methods to arithmetic correctness, protocols, security, low-power, CDC/RDC, and AI hardware verification.

Develop and execute verification strategies for a next-generation Physical AI SoC. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification flows. Verify digital blocks, memory systems, interconnects, processors, DMA engines, and complete HW/SW behavior. Perform performance, latency, QoS, emulation, FPGA prototyping, pre-silicon bring-up, post-silicon debugging, and hardware-software root-cause analysis.

Lead system-level design verification for a next-generation Physical AI SoC from verification planning through sign-off and tape-out. Own verification architecture, coverage goals, regressions, and risk tracking while coordinating boot, security, clock/reset, low-power, IO, and memory subsystem verification. Build and guide a verification team, remain hands-on in SystemVerilog and UVM, and partner with architecture, RTL, firmware, software, CAD, and infrastructure teams on simulation, emulation, and pre-silicon bring-up.

Own front-end semiconductor design and verification automation from RTL entry through DFT and implementation handoff. Responsibilities include RTL build, lint, CDC, formal, register generation, simulation, regressions, coverage, emulation, FPGA prototyping, and AI-assisted tooling. The role also manages EDA tool versions, distributed compute, flow health, maintenance, and collaboration with design, verification, DFT, and physical design teams.

Leads IT infrastructure and operations across hybrid cloud, on-premises, HPC, engineering compute, storage, networking, security, CI/CD, and employee technology. Owns capacity planning, disaster recovery, IAM, endpoint security, compliance readiness, service desk operations, budgets, vendors, and facilities technology. Manages and grows the IT team while supporting semiconductor and AI engineering workloads, protecting design IP, and ensuring infrastructure readiness for tape-outs and product releases.

Design and optimize RTL for key portions of a next-generation Physical AI SoC. Own significant blocks through microarchitectural definition, implementation, optimization, and tapeout while collaborating with architecture, software, verification, and physical design teams. Contribute to compute engines, memory subsystems, interconnects, DMA, control processors, and power-management logic. Analyze performance, power, and area tradeoffs, lead design reviews, debug complex systems, and mentor junior engineers.

Define and build the software architecture underlying Velaura’s Physical AI platform, including SDKs, runtimes, drivers, firmware, compilers, developer tools, and workload orchestration. Lead hardware/software co-design, performance optimization, profiling, and integration with ROS2, DDS, robotics, drones, and autonomous systems. Establish engineering processes and help develop a high-performing platform software team enabling efficient AI deployment across heterogeneous computing systems.