Top Tech Jobs & Startup Jobs

Design and implement embedded and system-level software for the Wafer Scale Engine, including Linux BSP, administrative services, hardware monitoring, debugging, and cross-team collaboration to improve reliability, observability, and operability at datacenter scale.

Build and productionize a GPU-accelerated prefill serving path for LLM inference: deploy, operate, and optimize model-serving, runtime (vLLM/PyTorch/ROCm), multi-node GPU infrastructure, reliability, performance, correctness, and benchmarking.

Lead development and execution of verification strategies and reusable UVM/SystemVerilog testbenches. Implement tests, manage regressions, gather coverage, and debug issues across simulation, emulation, gate-level and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and validation to improve verification infrastructure and methodology.

Develop and maintain infrastructure to build, test, operate, simulate, and evaluate Cerebras software. Design scalable automation workflows for cloud and datacenter, manage CI/CD, containerized deployments, and monitor software quality and performance on the Wafer Scale Engine.

Implement and scale LLM training, fine-tuning, and post-training techniques (RL-based). Build evaluation and data pipelines, debug ML stack issues, optimize training/inference workflows, and ship maintainable ML infrastructure code.

Lead technical direction and architecture for a multi-region Inference Cloud Platform. Define failure domains, service boundaries, and SLO-driven reliability. Optimize latency, throughput, and capacity for high-QPS ML inference workloads; implement graceful degradation (circuit breaking, backpressure, load shedding). Write and review production code, drive observability and incident response, and coordinate cross-team platform decisions. Mentor engineers and set long-term platform strategy.

Lead capacity planning and fleet strategy for the Inference Service: build rolling forecasts, support datacenter bring-up, decide model/cluster allocation, run utilization reporting, drive capacity tool adoption, coordinate cross-functional execution, and manage incident postmortems.

Design and implement verification strategies and reusable SystemVerilog/UVM testbenches; create tests, run regressions, collect coverage, and debug across simulation, emulation, and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and validation teams while improving verification infrastructure and methodologies.

Lead front-end RTL engineer responsible for functional specification, micro-architecture, RTL development, synthesis, and integration. Manage external ASIC vendors, collaborate with PD, verification, DFT, software and system teams, and debug silicon-level functional, timing, and power issues during bring-up to meet PPA and test coverage goals.

Lead Cerebras's model portfolio: decide which models ship, set quality standards and benchmarks, partner with model labs and open-source maintainers, drive model launches, enable customers, prioritize optimizations, and coordinate cross-functional teams to maximize inference performance and adoption.