Top Tech Jobs & Startup Jobs

Own and grow Cornelis Networks’ strategic relationship with Lenovo. Develop account plans, lead QBRs and executive engagements, identify co-selling opportunities, coordinate joint go-to-market initiatives, forecast revenue in Salesforce, and represent the company at events. The role requires expertise in AI/HPC ecosystems, OEM partnerships, enterprise sales, interconnect technologies, and cross-functional stakeholder influence. This remote U.S. position requires 50% travel, with preference for Raleigh-area candidates.

Design and implement RTL for high-speed ASIC data paths and packet-processing logic using Verilog and SystemVerilog. Collaborate on verification, timing constraints, physical design, post-silicon validation, system debugging, and power-aware performance optimization for AI and HPC networking systems.

Develop and maintain AI-based ASIC verification automation flows, regression infrastructure, dashboards, reporting tools, and triage automation. Build scripts and integrations using Python, Perl, Tcl, shell scripting, and Make. Support simulation, coverage, lint, formal, emulation, continuous integration, EDA tool integration, and distributed compute infrastructure. Debug automation, tool, runtime, licensing, queue, and workflow issues while improving verification reliability, reproducibility, and efficiency across geographically distributed engineering teams.

Develop and support hardware and software manufacturing test processes for networking products produced through contract manufacturers. Responsibilities include designing PCB test fixtures, creating functional test procedures, troubleshooting production and RMA failures, supporting NPI transitions, training manufacturing teams, managing test software releases, performing failure analysis, and maintaining test documentation. The role also involves hands-on electronic troubleshooting, assembly rework, prototype support, and collaboration between engineering and manufacturing.

Design and implement advanced Ethernet protocols for next-generation ASICs used in AI and HPC networking. Responsibilities include writing microarchitecture specifications, defining timing constraints, collaborating on timing optimization and verification planning, ensuring design coverage, and debugging post-silicon issues with hardware, firmware, and software teams.

Lead and grow the RTL design engineering team responsible for next-generation networking ASICs. Own RTL delivery schedules, coordinate design verification, emulation, and physical design dependencies, manage timing-closure and tape-out readiness, identify schedule risks, and allocate resources. Develop headcount and organizational plans, lead hiring, and scale globally distributed engineering practices while contributing hands-on expertise in microarchitecture, RTL design, synthesis, verification, and PPA optimization.

Verify RTL for advanced ASICs and SoCs at block, unit, and system-on-chip levels. Develop UVM testbenches, write and execute verification tests, analyze functional and code coverage, perform block-level formal verification, and support post-silicon verification. The role requires validating complex SoCs with multiple clock and reset domains and using scripting languages for verification automation.

Lead end-to-end PCIe IP integration into complex ASIC and SoC designs, collaborating across architecture, verification, physical design, software, and external IP vendors. Optimize PCIe performance, contribute to IO and interconnect architecture, and lead silicon bring-up, interoperability testing, and debugging across RTL, gate-level, emulation, and post-silicon environments. Mentor engineers and establish PCIe subsystem development practices for high-performance AI and HPC platforms.

Leads verification closure for ASIC modules, subsystems, and SoCs used in AI and HPC networking. Defines verification strategies, develops UVM testbenches, executes functional tests, manages regression and coverage closure, debugs RTL issues, and collaborates with design, software, emulation, hardware, and post-silicon teams. Provides technical leadership, mentoring, coding guidance, and promotes AI tools for verification productivity.

Lead verification closure for complex ASICs and SoCs used in AI and high-performance computing networking. Define verification strategies, develop UVM/SystemVerilog testbenches, execute functional testing, debug RTL failures, and close functional and code coverage. Guide block, subsystem, and SoC verification while collaborating with design, software, emulation, hardware, and post-silicon teams. Mentor engineers, establish verification guidelines, and promote AI tools to improve team productivity.