Own the microarchitecture and synthesizable RTL design of production memory subsystems for AI ASICs. Design DDR, LPDDR, and HBM controllers, cache hierarchies, memory-side accelerators, scheduling, ECC, QoS, and interfaces. Drive RTL through lint, CDC, synthesis, timing, area, and power closure; collaborate with verification, software, ML, and physical design teams. Support FPGA prototyping and AI-driven design automation using SystemVerilog and Python.

Lead microarchitecture and RTL design for on-chip interconnects and high-speed fabric. Own NoC/router/crossbar architecture, AMBA-compliant interconnects, HSIO bridges (PCIe/CXL/UCIe), peer-to-peer DMA engines, RTL infrastructure, FPGA prototyping, and verification collaboration to achieve low-latency, high-bandwidth, deadlock-free SoC communication and production tapeout readiness.