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Design and implement RTL and microarchitectural components for high-performance SoC/IP. Develop SystemVerilog/Verilog modules, optimize PPA, collaborate with verification and physical design teams, support IP integration and silicon bring-up, and contribute to documentation and methodology improvements.

Lead development, optimization, and verification of digital silicon IP. Create and maintain specifications and documentation. Characterize IP performance using FPGA simulation and emulation and collaborate with architecture, PD, and software teams from design through bring-up.

Lead SoC architecture definition for next-generation compute platforms. Drive tradeoffs across performance, power, area, bandwidth and latency; define memory hierarchy, NoC/interconnect, coherency, and subsystem partitioning. Lead performance modeling and workload analysis (C/C++/SystemC), integrate third-party IPs, collaborate with RTL, verification, physical design, firmware and software teams, support silicon bring-up, debugging, validation and roadmap planning.

Lead architecture definition and technical direction for next-generation GPUs. Define data-parallel microarchitecture and memory/coherency hierarchies, drive tradeoffs (performance/power/area), perform workload profiling and performance modeling, collaborate across RTL/verification/physical/firmware/software teams, support silicon bring-up and post-silicon tuning, and contribute to long-term roadmap planning.

Plan and oversee low-level software and driver development for graphics processors. Manage schedules, risks, deliverables, and cross-team coordination; report progress to stakeholders; improve PM processes; coordinate with other PMs; communicate closely with engineers and executives. On-site 3-4 days/week in the Bay Area with occasional travel.

Lead enterprise master data architecture and PLM implementation, design item master and lifecycle schemas, build data quality and ETL pipelines, integrate CAD/EDA and PLM with ERP/MES, oversee data governance, BOM audits, and supply-chain data syndication for high-volume semiconductor manufacturing.

Plan and oversee SoC/IC chip design programs, manage schedules and risks, coordinate global teams and other PMs, report progress to stakeholders, and improve PM processes to meet product goals.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Lead Philippines finance and operations: manage GL/AP/AR, month/quarter/year-end close, inventory/COGS and equipment depreciation, prepare PFRS/IFRS financial statements, ensure BIR/SEC tax compliance and filings, handle audits, design SOPs and internal controls, leverage NetSuite/cloud ERP to automate reporting and support cross-functional budgeting and inventory tracking for a distributed team.

Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.