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Own SoC, subsystem, and IP architecture from requirements through specification and tapeout. Build performance, power, and area models; define memory hierarchies, interconnects, and interfaces; and lead architecture reviews. Write specifications for RTL, verification, and physical design teams, collaborate with ML researchers on AI-assisted architecture exploration, and translate customer requirements into silicon.

Own block-level and full-chip physical implementation from netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, timing, power, congestion, physical verification, and signoff. Build automation for place-and-route flows, evaluate AI-generated physical design decisions, and collaborate with semiconductor customers on implementation challenges.

Own DFT architecture and implementation for SoCs and IP, including scan, compression, MBIST, LBIST, boundary scan, ATPG, verification, and timing closure. Support silicon bring-up, pattern debugging, yield analysis, automation, and coverage reporting. Collaborate with RTL, synthesis, physical design, test, and product engineering teams while helping develop AI-assisted DFT methodologies.

Build and maintain semiconductor design flows spanning RTL, synthesis, static timing analysis, place and route, and signoff. Integrate Synopsys and Cadence EDA tools with AI agents and data pipelines, develop regression and reporting infrastructure, manage EDA licensing and compute scheduling, curate design data with ML researchers, and support secure on-premises customer deployments.

Own physical verification and reliability signoff for production semiconductor tapeouts. Responsibilities include DRC, LVS, ERC, antenna, IR drop, electromigration, and power integrity analysis; debugging violations; managing tapeout checklists and foundry deliverables; building automation; and developing AI-assisted signoff triage and repair workflows.

Design and own production RTL for IP blocks and subsystems, from microarchitecture through signoff. Responsibilities include SystemVerilog implementation, lint, CDC/RDC, synthesis, timing closure, verification collaboration, assertions, coverage, and debugging across simulation, emulation, and silicon. The role also evaluates AI-generated RTL and collaborates with semiconductor customers. Required experience includes taped-out chip designs, strong RTL and microarchitecture expertise, scripting, and familiarity with standard hardware protocols.

Build and maintain SoC and subsystem emulation and FPGA prototyping platforms. Map designs to emulators and FPGAs, perform partitioning and timing closure, support software bring-up and system validation, debug hardware/software issues, automate compilation and triage, and generate system-level data for AI model training and evaluation.

Own power intent from architecture through signoff for SoCs and IP. Define UPF, implement power and clock gating, manage voltage domains and retention, run power-aware simulation and low-power checks, perform CDC/RDC analysis, support power estimation and closure, automate reporting, and evaluate AI-generated power intent.

Own RTL-to-netlist synthesis and timing closure for production silicon programs. Develop SDC constraints, perform signoff static timing analysis across corners and modes, conduct logic equivalence checking, and automate synthesis and timing workflows. Evaluate AI-generated constraints and timing fixes while collaborating with RTL and physical design teams. The role requires 5+ years of production tapeout experience and expertise with major synthesis, timing, equivalence-checking, Tcl, and Python tools.

The Special Projects Lead at Voltai manages complex, independent projects, collaborates with leadership, and drives innovative solutions in a fast-paced startup environment.