Top Tech Jobs & Startup Jobs

Own end-to-end FPGA and ASIC development from microarchitecture and SystemVerilog RTL through implementation, timing closure, simulation, and lab validation. Design networking and digital logic functions, build FPGA prototypes, bring up systems combining FPGA, firmware, and software, and optimize cost, size, power, performance, and features for AI inference platforms.

Designs and implements Go-based control-plane software for custom AI inference hardware. Responsibilities span system management APIs, Linux services, hardware interfaces, diagnostics, observability, security, firmware updates, distributed systems, and workload management. The role requires hands-on debugging across application, operating system, firmware, and hardware boundaries, plus technical leadership, mentoring, architecture, and production ownership. Regular on-site lab work includes server racking, system bring-up, hardware troubleshooting, and documentation.

Own full-cycle recruiting for specialized hardware engineering roles, including ASIC, RTL, verification, physical design, DFT, and silicon validation. Partner with engineering leaders to define hiring needs, source passive candidates, manage interviews, close experienced engineers, and improve recruiting operations. Use pipeline data, recruiting tools, LLMs, and agentic AI to increase efficiency while maintaining human-centered candidate engagement.

Define multi-generation hardware/software architectures for AI inference silicon, including boot, memory, DMA, scheduling, security, telemetry, and host/device interfaces. Integrate firmware, Linux, runtimes, simulation, and developer tooling; lead architecture reviews; resolve cross-team technical issues; prototype high-risk interfaces; and mentor senior engineers. The role requires deep systems expertise, strong C or C++ skills, and architecture-level ownership across pre-silicon, silicon bring-up, and production software.

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.

Own synthesis, timing closure, constraint development, and implementation readiness for ASIC accelerator partitions. Execute Cadence Genus or Synopsys Design Compiler flows, develop SDC and MMMC environments, optimize timing, area, power, and congestion, and collaborate with RTL, verification, DFT, physical design, and backend teams. Improve synthesis methodology, analyze QoR and timing bottlenecks, support vendor partners, and apply AI tools to engineering automation and report analysis.

Leads microarchitecture, RTL implementation, and signoff for complex IP blocks and subsystems in AI inference ASICs and SoCs. Owns PPA optimization, interface and memory integration, lint, CDC/RDC, DFT, synthesis, and timing closure. Collaborates with architecture, verification, physical design, and vendors; develops design methodologies and automation; supports silicon bring-up and customer engagements; and mentors junior engineers while driving technical decisions.

Own end-to-end DFT architecture and implementation for AI accelerator ASICs, including scan, compression, ATPG, MBIST, boundary scan, IJTAG, verification, and physical-design integration. Drive pre-silicon coverage, timing and power-aware test implementation, silicon bring-up, and cross-functional execution through tapeout. The role requires hands-on RTL, synthesis, gate-level verification, Tessent tool expertise, scripting, and failure analysis across multiple production tapeouts.

Lead the microarchitecture, SystemVerilog RTL design, integration, optimization, and signoff of complex ASIC and SoC IP for AI inference hardware. Own PPA targets, interfaces, memory integration, verification collaboration, DFT, CDC/RDC, synthesis, timing closure, and post-silicon support. Establish design methodologies, mentor engineers, lead technical reviews, and drive cross-functional architectural decisions.

Build simulation and modeling infrastructure for AI inference accelerators before silicon availability. Develop analytical performance models, functional and timing simulators, virtual platforms, and software integrations. Validate functionality and performance against reference implementations and hardware, improve simulator speed and usability, and create automated regression coverage. Collaborate with hardware, compiler, firmware, runtime, performance, and test engineers to support architecture exploration and realistic software workloads.