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Lead synthesis, timing convergence, and implementation readiness for AI accelerators. Own synthesis flows, SDC constraints, timing closure, physical-aware optimization, vendor coordination, and apply automation/AI to improve QoR and timing debug across multi-million-gate designs.

Lead physical implementation of AI accelerator ASICs from floorplanning through tapeout. Drive placement, CTS, P&R, signal/IR/EM closure, signoff, and methodology development. Partner with RTL, synthesis, DFT, package, and backend teams to deliver timing, power, area, congestion, and yield targets, and apply AI techniques to optimize QoR.

Lead architecture and performance exploration for next-generation AI inference accelerators. Build analytical models and simulation frameworks, define subsystem interfaces and roadmaps, and drive hardware/software co-design with compiler, runtime, ML, and silicon teams to optimize latency, throughput, memory, interconnects, power, and cost for evolving LLMs and transformer-based workloads.

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.

Lead pre-silicon emulation strategy for a next-generation AI inference ASIC using Cadence Palladium. Architect multi-rack models, enable software left-shift via hybrid emulation, verify high-speed interfaces and memory hierarchies, perform power/performance analysis, and collaborate with RTL, DV, software teams and Cadence R&D to ensure silicon readiness.

Lead end-to-end DFT/DFx strategy and hands-on implementation for AI inference ASICs: define DFT architecture, integrate into RTL and third-party IP, drive ATPG/BIST/scan verification through tapeout, partner with physical design and external vendors, and support silicon bring-up.

The Senior Software Engineer will develop high-performance software for executing open-source LLMs on custom hardware, focusing on optimizations and efficient libraries primarily in C++.