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Contribute to physical implementation of AI accelerator ASICs from floorplanning and macro placement through tapeout. Responsibilities include clock tree synthesis, place and route, timing, power, signal integrity, IR/EM, DRC, LVS, congestion, ECOs, metal fill, and signoff closure. The role also supports implementation methodology, advanced-node tapeouts, AI-enabled QoR analysis, and collaboration with RTL, synthesis, DFT, package, and backend teams.

Owns AI-assisted engineering across accelerator software teams, embedding agentic workflows into coding, debugging, triage, testing, documentation, CI, and silicon-debug processes. Builds shared agent tooling, maintains evaluations, measures productivity gains, and establishes standards for reliable AI-native development. Requires expert experience with Codex, Claude Code, LLM APIs, evaluations, and adopted developer tooling, plus strong systems or infrastructure credibility.

Lead the architecture, design, verification, physical implementation, tape-out, validation, and production ramp of high-performance AI inference ASICs. Drive PPA optimization, memory subsystem design, hardware/software co-design, and relationships with foundries, IP vendors, and EDA providers. Recruit and mentor the ASIC team while shaping the company’s silicon roadmap and execution methodology.

Define next-generation AI inference accelerator architectures through architectural exploration, performance modeling, hardware/software co-design, and ASIC specification. Evaluate transformer, MoE, sparse, long-context, and emerging AI workloads; model latency, throughput, memory, bandwidth, power, area, cost, and scaling; define subsystem interfaces; and guide the product roadmap in collaboration with software, ML, systems, and silicon teams.

Owns synthesis methodology, timing closure, constraint development, QoR optimization, and implementation readiness for advanced AI accelerator ASICs. The role transforms RTL into implementation-ready netlists, leads physical-aware optimization and timing budgeting, collaborates across architecture, verification, DFT, and backend teams, and provides technical leadership to external implementation partners. Responsibilities also include developing Tcl and Python automation and applying AI to improve timing analysis, regression, debugging, and engineering workflows.

Develop and lead verification strategies for AI inference ASICs, including SystemVerilog UVM environments, simulation testbenches, directed and constrained-random testing, coverage closure, debugging, and root-cause analysis. Collaborate with design, architecture, software, FPGA, and emulation teams across pre-silicon and post-silicon validation. Manage verification schedules, deliverables, and risk mitigation while helping ensure functional correctness and performance.

Lead ASIC/SoC IP and subsystem development from microarchitecture through RTL signoff. Design parameterized SystemVerilog RTL, own PPA targets, and lead lint, CDC/RDC, DFT, synthesis, and timing activities. Architect interfaces, DMA, coherency, and HBM/DDR integration while collaborating with architecture, verification, and physical design teams. Improve design methodologies, mentor engineers, lead reviews, support post-silicon debug, and contribute automation flows.

The Senior Software Engineer will develop high-performance software for executing open-source LLMs on custom hardware, focusing on optimizations and efficient libraries primarily in C++.

Lead architecture and performance exploration for next-generation AI inference accelerators. Build analytical models and simulation frameworks, define subsystem interfaces and roadmaps, and drive hardware/software co-design with compiler, runtime, ML, and silicon teams to optimize latency, throughput, memory, interconnects, power, and cost for evolving LLMs and transformer-based workloads.

Lead synthesis, timing convergence, and implementation readiness for AI accelerators. Own synthesis flows, SDC constraints, timing closure, physical-aware optimization, vendor coordination, and apply automation/AI to improve QoR and timing debug across multi-million-gate designs.