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Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.

The RTL Engineer will collaborate on the design and productization of Ethernet devices, perform RTL coding, debugging, and post-silicon validation with a focus on networking ICs.

The Engineering Program Manager will lead complex product development programs, manage cross-functional execution, coordinate schedules, and drive communication among teams and external partners.

Lead DFT architecture for multi-chip systems SOC, managing test design functions and supervising ATPG generation while ensuring performance standards.

The role involves validating Linux BSPs for stability and performance, developing test plans, automating tests, collaborating with teams, and ensuring quality for next-gen networking products.

Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.