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Lead the DFT architecture of multi-chip systems, oversee test design functions, manage ATPG generation, and ensure high coverage goals. Collaborate with advanced DFT techniques, drive performance, and utilize various CAD tools.

Responsible for developing diagnostic software and tools for hardware validation, collaborating with teams for board validation, and conducting root cause analysis.

The Staff RTL Engineer will design high-speed networking devices, optimize memory management, ensure compliance with standards, and collaborate with various teams for performance optimization and troubleshooting.

The role involves designing and architecting microarchitecture for Ethernet packet processing, collaborating with teams, conducting feasibility studies, and verifying designs for performance optimization.

Define physical assembly of SOC, perform P&R, timing, and design analysis. Collaborate with micro-architects on performance tradeoffs and validate design processes.

Lead the architecture and development of SAI with SONiC, manage SDK development, and ensure integration with hardware, while overseeing automated tests and collaborating with teams.

Design and implement high-speed networking chips focusing on packet buffering, performance optimization, and protocol support, ensuring compliance with standards and conducting thorough testing.

The Hardware Engineer will be responsible for developing systems and sub-assemblies from concept to production, involving hardware definition, design, qualification, and collaboration with multiple teams.

Lead the design and implementation of packet processing architectures for high-performance networking ASICs, collaborating with various engineering teams to meet system requirements and optimize performance.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.