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The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.

Lead DFT architecture for multi-chip systems SOC, managing test design functions and supervising ATPG generation while ensuring performance standards.

The role involves post-silicon bring-up, debugging, and validation of ASICs, focusing on diagnostic infrastructures and automation frameworks.

The Technical Leader for Network SDK QA will manage the quality and reliability of the platform software, defining QA strategy, designing test frameworks, and mentoring QA engineers. Responsibilities include leading testing processes, collaborating cross-functionally, and driving automation coverage.

Lead ASIC chip design from micro-architecture to full-chip integration, emphasizing RTL development, verification collaboration, and timing closure.

Lead the simulation and analysis of AI communication workloads, optimizing performance and collaborating with customers and ASIC designers to enhance AI networking solutions.

The RTL Engineer will collaborate on the design and productization of Ethernet devices, perform RTL coding, debugging, and post-silicon validation with a focus on networking ICs.

The Physical Design Engineer will manage SOC physical assembly, design methodologies, and collaborate with engineers to optimize performance, power, and area for AI infrastructure solutions.