Open application for multiple functions at a Dutch neuromorphic semiconductor startup. Candidates should have domain expertise (engineering, product, commercial or corporate), collaborate across disciplines, communicate effectively internationally, and contribute to fast-moving, innovative projects across chip design, embedded and AI/ML software, product, and commercial roles.

Lead development and maintenance of SystemVerilog/UVM verification environments for module and SoC levels. Create tests, define functional coverage, drive constrained-random stimulus, debug RTL using waveform tools, automate EDA flows, and mentor a small team to ensure coverage closure and release readiness.

Manage the delivery of software projects across multiple teams, optimize processes, ensure quality standards, and lead cross-functional collaboration.