Top Tech Jobs & Startup Jobs

Lead design and verification of high-speed analog and mixed-signal circuits (ADCs, DACs, PLLs, TIAs, SerDes, optical drivers) through tape-out and post-silicon bring-up in advanced FinFET or SOI processes. Collaborate cross-functionally, create documentation, present to leadership, and mentor junior designers.

Manage ERP and subsidy management projects, oversee risks, issues, project charters, stakeholder engagement, and release cycles (semi-annual Workday releases). Ensure compliance with SOX/SDLC controls and coordinate with Agile Delivery Leads across Scrum and Kanban teams.

This role involves driving new client acquisition and revenue growth through full-cycle sales execution and relationship building with stakeholders, while maintaining pipeline tracking in CRM.

Lead RTL-to-GDSII implementation on advanced-node digital designs, driving PPA and quality-of-results. Own flows, debug complex issues, collaborate with CAD/design/program teams, mentor juniors, adopt new tools and ML techniques, and engage EDA vendors to resolve root causes.

Develop synthesizable RTL from micro-architecture, write bare-metal firmware for on-chip RISC CPUs, drive pre-silicon simulation and hardware-software co-verification, lead synthesis/timing closure and equivalence checking, build emulation environments, and perform silicon bring-up and post-silicon debug while collaborating across analog, verification, and physical-design teams.

Lead block-level physical design for analog/mixed-signal and high-speed interfaces (SerDes, PAM4). Own floorplanning, placement, routing, parasitic-aware layout, signoff checks (DRC/LVS/ERC/EM/IR), and top-level integration. Collaborate with designers, packaging, process, and product teams; support tapeout readiness, CAD automation, mentoring, and post-silicon debug to deliver manufacturable, high-performance IC layouts.

Senior individual contributor or technical lead designing and verifying high-speed analog and mixed-signal ICs (ADCs, DACs, PLLs, TIAs, laser/modulator drivers, SerDes). Drive transistor-level design and layout in advanced FinFET/SOI processes, lead pre-/post-silicon validation, collaborate with cross-functional teams, document results, and mentor junior designers.

Design and implement synthesizable RTL for high-speed interconnect ASICs, drive synthesis/timing closure, develop bare-metal firmware for embedded RISC CPU IP, lead pre-silicon simulation, emulation, and silicon bring-up, and collaborate across verification, physical-design, analog, and DSP teams to debug and integrate hardware-software systems.

Lead and execute analog/mixed-signal IC design for high-speed interconnects from architecture through tape-out and bring-up. Manage and mentor a design team, coordinate external contractors and IP vendors, design/verify SerDes front-ends, optical drivers, ADC/DACs, and transistor-level schematics in advanced FinFET/SOI nodes, drive pre-silicon simulation and post-silicon debug to meet PPA targets.

The role involves design verification of IP/SoC with hands-on experience in verification methodologies, particularly UVM/OVM, and requires strong problem-solving skills in a fast-paced environment.