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Lead end-to-end ASIC package architecture for FC-BGA and MCM solutions, driving trade studies, substrate stack-ups, SI/PI and thermal strategy, vendor engagement, qualification, and production ramp while defining organizational packaging standards and co-optimizing with silicon, RF, and systems teams.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Own RTL-level scan/MBIST/LBIST insertion, ATPG flow development, coverage closure, pattern optimization, and DFT verification/signoff. Integrate mixed-signal test strategies, collaborate with RTL/DV/PD teams, support silicon bring-up and failure analysis, and improve DFT methodology and automation.

Define and execute verification plans for block-to-full-chip, build SystemVerilog/UVM testbenches, write assertions, run constrained-random and directed tests, manage regressions and CI, perform coverage closure and debug, support silicon bring-up and post-silicon validation, and collaborate across architecture, RTL, DFT, firmware, and physical design teams.

Lead ASIC package architecture and detailed FC-BGA/MCM design for high-pin-count, power-dense SoCs. Drive package trade studies (SI/PI, thermal, manufacturability), define standards, partner with silicon/RF teams, engage OSATs and vendors, and support qualification and production ramp.

Lead end-to-end RTL-to-GDSII physical implementation for high-performance SoCs for satellites. Drive timing closure, PPA optimization, tool/flow decisions, manage external PD partners, collaborate with packaging, DFT, and post-silicon teams, and support production and spaceflight tapeouts in advanced FinFET nodes.

Lead ASIC package architecture and detailed FC-BGA/MCM package designs for high-pin-count, high-speed, power-dense SoCs. Drive package trade studies (SI/PI, thermal, manufacturability, reliability), define standards, collaborate with silicon/RF/systems teams, work with OSATs and substrate vendors, and support qualification and production ramp.

Develop and execute verification plans for block, subsystem, and full-chip designs. Build SystemVerilog/UVM testbenches, write SVAs, integrate formal checks, run constrained-random and directed tests, manage regressions and CI/simulation farms, perform failure triage and root-cause, implement coverage closure, and collaborate across RTL, DFT, firmware, and silicon validation teams.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.

Lead end-to-end Type‑1 cryptographic architecture for spacecraft and ground systems, from concept through NSA certification and on‑orbit operations. Define COMSEC, key management/loading, integrate crypto across flight software, avionics, RF, and ground, produce certification artifacts, mitigate cryptographic and supply‑chain risks, and establish reusable standards for high‑volume satellite production.