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Define and drive silicon domain subsystem architecture for next-generation FPGAs, focusing on security (Root of Trust, secure boot), FPGA configuration, microarchitectural features, hardware/software integration, validation/test planning, modeling and simulation, and cross-functional collaboration to deliver secure, high-performance, and power-efficient silicon solutions.

Lead functional logic verification of FPGA designs: develop verification plans, testbenches, and environments; execute simulations, debug pre-silicon issues, analyze power/timing, improve verification infrastructure, and collaborate with architects, RTL and physical design teams for coverage and integration.

Perform physical design implementation of custom IP and SoC from RTL to GDS, including synthesis, place-and-route, CTS, floorplanning, STA, power/noise analysis, and layout verification. Lead verification and signoff (formal equivalence, STA, power integrity, DRC/LVS, reliability). Analyze results, fix violations, optimize power/frequency/area, and improve physical design methodologies and automation.

Develop and support DSP Builder and improve the HLD compiler stack. Analyze design bottlenecks, implement compiler optimizations, and benchmark FPGA-targeted generated hardware, combining compiler software development with digital hardware design.

Lead product development from pre-silicon design through post-silicon validation; define and optimize full-chip test methodologies and on-chip DFT strategies; drive technical innovation and process improvements; mentor and develop engineers; collaborate with global design, software, manufacturing, and product teams; and proactively manage technical risk to ensure product quality and timely delivery.

Define and drive architecture for high-speed external memory and general-purpose IO subsystems (DDR, LPDDR, MIPI, LVDS, ONFI). Lead cross-functional teams from concept through silicon bring-up, optimize PPA and usability with Quartus integration, perform trade-off analysis, and engage customers and partners to influence product roadmaps.

Develop and maintain automation and methodologies for EMIR analysis in silicon design, ensuring power integrity and reliability closure. Collaborate with cross-functional teams to define criteria and drive project-level signoff, while also evaluating and improving EMIR tools and methodologies.

Lead global teams in semiconductor hardware engineering, focusing on chip package and board development, power and reliability engineering, and strategic vendor management.

The FPGA Silicon Design Verification Engineer performs verification of FPGA designs, develops verification plans, analyzes simulations, debugs issues, and collaborates with teams to ensure functional compliance.

Define end-to-end robotics system architectures across sensing, perception, localization, planning, control and actuation. Lead customer technical engagements, deliver architecture proposals, PoC/prototyping, demos, and market strategy. Produce reference architectures, white papers, and training materials.