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Provide technical leadership for Ethernet IP bring-up, validation, and customer support across 10G–100G speeds. Debug designs, validate protocol compliance (AN/LT, IEEE 1588 PTP), create reference designs and documentation, collaborate with cross-functional teams, and drive root-cause analysis to transition designs from prototype to production.

Optimize and transform Workday Recruiting processes: improve recruiter efficiency, streamline approvals and scheduling, build reporting and dashboards, identify automation/AI opportunities, and partner with TA/HR stakeholders to implement scalable recruiting solutions.

Provide customer-facing technical leadership for Ethernet FPGA IP: lead design bring-up and validation across 10G–800G, debug and optimize performance, validate protocol compliance (AN/LT, IEEE1588 PTP), produce reference designs and documentation, and collaborate with design, validation, product engineering, and sales to resolve issues and improve IP quality.

Lead design, verification, and optimization of high-speed interconnects. Develop simulation methodologies using EDA tools for electrical performance. Collaborate across design teams to meet performance goals.

Lead and grow an STA team responsible for timing closure and signoff of advanced FPGA designs. Define STA methodology and flows, drive timing analysis, debug violations, collaborate with RTL, synthesis, P&R and architecture teams, and deliver timing-driven PPA improvements and on-time closure across multiple programs.

Perform static timing analysis and timing signoff for FPGA/ASIC designs, debug and resolve timing violations, develop and validate timing constraints, collaborate with RTL/synthesis/physical design teams, and improve STA methodology and automation to optimize performance, power, and area.

Perform functional verification of FPGA designs by developing verification plans, testbenches, and environments (UVM/OVM). Run simulations, analyze power and timing, debug pre-silicon issues, and collaborate with architects, RTL and physical design teams. Maintain verification infrastructure, execute gate-level and power-aware strategies, and document verification results and reviews.

Develop and execute functional verification plans and testbenches for FPGA designs using SystemVerilog and UVM/OVM. Create verification environments, run simulations (including gate-level and power/timing-aware), root-cause and debug pre-silicon issues, collaborate with architects and RTL/physical design teams, and document verification strategy and results.

Drive product definition and roadmaps for PCIe, CXL, and DMA IP for FPGA devices. Gather and prioritize market and customer requirements, align cross-functional programs, generate product requirements, and coordinate engineering execution and change management to deliver hard and soft IP solutions.

Define and drive silicon domain subsystem architecture for next-generation FPGAs, focusing on security (Root of Trust, secure boot), FPGA configuration, microarchitectural features, hardware/software integration, validation/test planning, modeling and simulation, and cross-functional collaboration to deliver secure, high-performance, and power-efficient silicon solutions.