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Own end-to-end technical sourcing for advanced semiconductor and AI hardware roles. Build targeted talent searches, map technical talent pools, craft outreach to passive candidates, and develop long-term relationships. Partner with hiring managers and founders to understand complex technical requirements and create customized sourcing strategies. Use GitHub, LinkedIn, referrals, research communities, and X-Ray search. Track candidate pipelines, metrics, and funnel data while managing multiple complex searches with high quality.

Own end-to-end talent acquisition and headhunting for Arago’s technical hiring across France, North America, and Israel. Partner with the CEO, CTOs, and engineering leaders to define roles, source and close senior engineers, scientists, and technical leaders across hardware, optical, software, and research. Build proactive sourcing pipelines, improve interview processes and hiring standards, monitor pipeline health and hiring velocity, and communicate progress to leadership.

Own mixed-signal verification methodology, planning, and execution for digital-to-analog interfaces on SoCs. Build verification environments at block, subsystem, and SoC levels; develop tests, assertions, checkers, scoreboards, and coverage; verify analog control and configuration across operating conditions; run regressions, debug failures, and drive coverage to sign-off. Collaborate with analog, RTL, architecture, firmware, and SoC verification teams, and develop behavioral or real-number models for mixed-signal simulation.

Design and verify custom digital hardware and RTL components for AI and machine-learning compute platforms. Responsibilities include developing memory, control, and compute subsystems; creating functional verification infrastructure; collaborating with software and architecture teams; supporting synthesis, timing analysis, DFT, and backend integration; and contributing to hardware-software co-design and architectural exploration.

Design and deliver digital subsystems for mixed-signal ICs, including calibration engines, control logic, converters, multiplexers, and serial interfaces. Own the flow from RTL design and verification through synthesis, floorplanning, place and route, timing closure, physical signoff, and tape-out. Integrate external IP and collaborate with analog, layout, and system teams to resolve cross-domain issues and optimize high-speed digital-analog boundaries. SerDes experience is advantageous.

Arago is seeking ongoing applications for a dynamic range of roles related to AI and hardware, encouraging candidates to submit their details for consideration.

Lead system-level definition and delivery of next-generation multiphysics compute platforms: own architecture from concept to tape-out, drive modeling and specs, mentor RTL/verification/physical teams, collaborate with software and packaging, evaluate new directions and de-risk prototypes to ensure scalable, high-performance silicon.

Develop and optimize low-level computation software, kernels, runtime components, drivers, hardware abstraction layers, and firmware for custom AI accelerators using C/C++, assembly, and architecture-specific intrinsics. Collaborate with hardware and RTL teams on interfaces, memory systems, boot flows, and chip bring-up. Debug and validate software across simulation, emulation, FPGA, and silicon platforms while improving latency, throughput, memory usage, and deterministic performance.

Design and simulate high-performance analog and RF IC blocks (amplifiers, mixers, PLLs, ADCs/DACs), optimize for power/area/PVT, collaborate with optics/PCB/layout teams, guide physical design, and support post-silicon validation and lab bring-up.

Optimize execution and serving of modern AI models on Arago's custom accelerator by analyzing workloads, developing and tuning kernels and fused operators, designing multi-device mappings, implementing inference-serving techniques, and building profiling and benchmarking infrastructure while collaborating with hardware, compiler, and runtime teams.