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Design and implement embedded software connecting microcontrollers, FPGAs, and GPUs for deterministic, low-latency quantum control. Develop high-performance interfaces (DMA, PCIe, serial), real-time control on Linux/RTOS, build embedded Linux distributions, optimize SIMD performance, and ensure code quality, reproducible builds, and cross-disciplinary collaboration to support R&D.

Design and develop cryogenic systems for quantum computing, focusing on CAD models, prototyping, assembly, and FEA simulations.

The Senior Backend Engineer will design and implement backend services for a quantum computing job submission platform, ensuring scalability and security. Responsibilities include developing APIs, maintaining efficient data transfer objects, and collaborating with cross-functional teams.

Coordinate and deliver R&D and client projects for superconducting quantum processors. Plan, track, and manage multi-team schedules, budgets, risks, and deliverables; prepare reports for funders and clients and facilitate interdisciplinary collaboration across physics, nanofabrication, software, and cryogenics teams.

The Senior FPGA Engineer will design, implement, and verify FPGA systems for high-performance applications, collaborating with cross-functional teams.

Design, develop, and test hardware components and systems for superconducting quantum computers. Collaborate across teams, perform testing, and create documentation.

Working within the Quantum Hardware Team, design and test superconducting quantum processors, collaborating with teams, and communicating technical results.

The role involves re-architecting a large Python codebase with Rust for performance, designing robust representations, and ensuring code quality for quantum control systems.

Design and optimize pulse-level microwave control and calibration for superconducting qubits, build physics-based qubit models, deploy real-time FPGA-backed control solutions, and collaborate with AI teams to enable closed-loop calibration and robust, drift-resistant gate performance.

Define architecture for next-generation superconducting quantum processors, including qubit, coupling, control, and readout strategies. Analyze tradeoffs between coherence, connectivity, and control complexity, collaborate with fabrication, control, and calibration teams, and guide hardware roadmap decisions.