Top Tech Jobs & Startup Jobs

Lead BEOL process integration for an advanced photonic chip at the foundry in Leuven. Own BEOL process flows, SPC/specification management, DOE and process transfers, fault isolation and failure analysis (SEM/FIB/TEM/EDX), and drive yield, reliability, and continuous improvement while coordinating closely with foundry and internal design teams.

Leads end-to-end architecture, performance budgeting, interface control, supplier oversight, hardware and software alignment, laboratory integration, and bring-up of a multidisciplinary photonic computing prototype. Owns the prototype as a long-term experimental platform, designing impairment characterization campaigns, evaluating encoding schemes, maintaining calibration and measurement infrastructure, and translating results into future system architecture decisions.

Leads the analog, mixed-signal, RF, and mmWave IC design organization, from architecture and circuit design through tape-out, validation, qualification, yield ramp, and high-volume production. Builds and mentors the team, defines IP specifications, partners across photonics and systems engineering, drives design-for-manufacturability and test, and owns silicon performance, power, schedule, reliability, and production robustness.

Coordinates technical interview scheduling, onsite candidate experiences, travel logistics, debriefs, interviewer feedback, and ATS data integrity. Builds recruiting playbooks, templates, workflow standards, and interviewer training while improving hiring processes and candidate communication. Supports recruiting leaders and technical recruiters in a fast-growing startup environment, including managing overlapping priorities and confidential candidate information.

Own People Operations infrastructure for a rapidly scaling startup, including onboarding, multi-state employment compliance, HRIS administration, benefits, leave programs, policies, performance cycles, employee relations, offboarding, and international employment support. Partner with Finance, Legal, Recruiting, Facilities, and EHS on payroll, equity, workers’ compensation, and compliance matters. This is the company’s first dedicated People Operations hire and requires full-time onsite work in Austin.

Own the design-for-test architecture and strategy for complex ASICs, including ATPG scan, MBIST, boundary scan, JTAG, HBM, analog test, and wafer/package-level testing. Lead coverage assessment, signoff, test vector development, RTL and physical-design testability, production test-plan delivery, and post-silicon handoff. Establish the company’s DFT flow, metrics, and processes while collaborating with analog, operations, package, physical-design, and OSAT teams.

Own the end-to-end performance model for an optical vector-matrix multiplication engine. Build optical and electrical link budgets, behavioral signal-chain models, and accuracy, throughput, latency, and power allocations. Model noise, distortion, jitter, quantization, crosstalk, mismatch, and nonlinearities using Monte Carlo, corner, and time-domain simulations. Correlate models with laboratory and silicon measurements, lead trade studies, collaborate across engineering teams, mentor engineers, and contribute to patents.

Own calibration architecture, algorithms, system integration, laboratory bring-up, and verification for an optical vector-matrix multiplication engine. Develop control and optimization methods for optical phase, amplitude, and timing calibration; specify calibration hardware and software interfaces; lead hardware characterization and debug; correlate measurements with models; define diagnostics and verification plans; and mentor engineers. The role requires extensive hands-on work with electro-optic or mixed-signal systems, test equipment, automated measurement software, and cross-functional design teams.

Leads design verification methodology and team development for complex compute ASICs. Owns UVM testbench architecture, multi-level verification planning, VIP integration, gate-level simulation, FPGA-based verification, cloud-hosted emulation, formal verification, coverage closure, and AI-assisted testbench development. Partners across architecture, RTL, physical design, DFT, and validation to drive tapeout readiness.

Lead the end-to-end electronic IC program from architecture and specification through ASIC design, verification, tapeout, post-silicon bring-up, and production readiness. Coordinate internal engineering teams and external foundry, IP, OSAT, and design-service partners. Own schedules, dependencies, risks, readiness reviews, tapeout logistics, lab bring-up, silicon debug, and executive reporting. Establish AI-augmented program processes and drive cross-functional execution for a first-silicon mixed-signal ASIC supporting optical AI compute.