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Reposted 4 Hours AgoSaved
In-Office
Santa Clara, CA, USA
77K-102K Annually
Mid level
77K-102K Annually
Mid level
Hardware • Semiconductor • Manufacturing
Coordinate recruiting operations and interview scheduling, maintain ATS accuracy, support offer processes and recruiting analytics. Proactively source and engage technical and early-career candidates, screen resumes, build pipelines, track sourcing metrics, and partner with recruiters and hiring managers to improve processes and candidate experience.
Top Skills: AtsCRMJob BoardsLinkedInRecruiting AnalyticsRecruiting PlatformsSourcing ToolsTalent Databases
2 Days AgoSaved
In-Office
Lviv, Lviv Oblast, UKR
Mid level
Mid level
Hardware • Semiconductor • Manufacturing
Coordinate recruiting operations and scheduling, maintain ATS accuracy, and support offer coordination. Proactively source technical and early-career talent, engage passive candidates, screen resumes, and build pipelines. Partner with recruiters and hiring managers on sourcing strategy, track pipeline and sourcing metrics, and support recruiting analytics, process improvements, and ad hoc talent projects to improve time-to-fill and candidate experience.
Top Skills: AtsAts/CrmJob BoardsLinkedInRecruiting AnalyticsRecruiting PlatformsSourcing ToolsTalent Databases
2 Days AgoSaved
In-Office
Taoyuan City, TWN
Mid level
Mid level
Hardware • Semiconductor • Manufacturing
Coordinate recruiting operations and interview logistics, maintain ATS accuracy, and support offer coordination. Proactively source and engage technical and early-career candidates, screen resumes, build pipelines, track sourcing metrics, and partner with hiring managers to improve recruiting processes and analytics.
Top Skills: AtsAts/CrmJob BoardsLinkedInRecruiting PlatformsSourcing ToolsTalent Databases
2 Days AgoSaved
In-Office
Munich, Bayern, DEU
Senior level
Senior level
Hardware • Semiconductor • Manufacturing
Design and implement digital logic for MEMS/CMOS timing products: create micro-architecture and RTL (Verilog/SystemVerilog), develop testbenches and SVA, define timing constraints, run synthesis/STA, fix timing, collaborate across teams, and support post-silicon bring-up and validation.
Top Skills: CdcDesign CompilerDigital Signal Processing (FirDpllFifoFsmGenusIir)MatlabMixed-Signal Digital DesignPerlPlace And RoutePrimetimePythonRtlSimulinkStatic Timing Analysis (Sta)SynthesisSystemverilogSystemverilog Assertions (Sva)TclVerilog
Reposted 4 Days AgoSaved
In-Office
Taoyuan City, TWN
139K-191K Annually
Senior level
139K-191K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Lead specification, design, development, and qualification of custom semiconductor packaging (QFN, WLCSP, substrate, ceramic, multi-chip). Manage package design, DoEs, OSAT development/prototyping, ensure performance/reliability/quality, and lead troubleshooting and release-to-production activities.
Top Skills: AutocadBumpingCeramic PackagesCmosDesign Of Experiments (Doe)DmaFlip-ChipLeadframe-Based PackagesMemsMulti-Chip ModulesOsatQfnSubstrate-Based PackagesTgaTmaWlcsp
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5 Days AgoSaved
In-Office
Ottawa, ON, CAN
96K-132K Annually
Senior level
96K-132K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Design and simulate high-performance CMOS analog and custom digital circuits for precision timing products. Prepare design reviews and documentation, collaborate with layout, digital, system, and validation teams, and test, debug, and characterize prototypes in the lab.
Top Skills: Analog/Mixed-Signal DesignBicmosCadence Analog/Mixed-SignalCmosDevice PhysicsLab Testing/CharacterizationMemsPhase-Noise
5 Days AgoSaved
In-Office
Ottawa, ON, CAN
131K-187K Annually
Senior level
131K-187K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Provide technical leadership and hands-on analog/mixed-signal CMOS circuit design for high-performance timing products. Design and develop PLLs, VCOs, phase detectors, and charge pumps; support prototyping, lab characterization, and post-layout verification; collaborate with cross-functional and remote teams; mentor junior designers and drive product development through production release.
Top Skills: AmsAnalog Mixed-Signal SimulationCadence (Analog/Mixed-Signal)Charge PumpCmosPhase DetectorPllPost-Layout VerificationSystemverilogVcoVerilog-A
5 Days AgoSaved
In-Office
Ottawa, ON, CAN
114K-157K Annually
Senior level
114K-157K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Lead analog/mixed-signal circuit design for high-performance timing products, from concept through production. Provide hands-on design of PLLs and related blocks, support prototype testing and lab characterization, collaborate with cross-functional and remote teams, and mentor junior designers.
Top Skills: AmsAnalog/Mixed-Signal CmosCadenceCharge PumpsPhase DetectorsPllsSystemverilogVcosVerilog-A
Reposted 6 Days AgoSaved
In-Office
Rijswijk, NLD
Senior level
Senior level
Hardware • Semiconductor • Manufacturing
Lead chip-level planning and perform block- and leaf-cell custom layouts for CMOS/BiCMOS circuits. Drive schematic-driven layouts, floorplanning, power and shielding, DRC/LVS/ERC verification, chip integration and tape-out. Mentor junior/offshore layout engineers and help establish layout methodologies, processes, and automation.
Top Skills: BicmosCadence PvsCadence VirtuosoCmosDesign ScriptsDrcErcLvsMentor CalibreTsmc 180NmTsmc 22NmTsmc 65Nm
Reposted 8 Days AgoSaved
In-Office
Santa Clara, CA, USA
154K-212K Annually
Senior level
154K-212K Annually
Senior level
Hardware • Semiconductor • Manufacturing
The SEC Reporting, SOX & ESG Compliance Manager prepares SEC filings, manages SOX compliance, and coordinates ESG reporting, collaborating across functions for process improvement.
Top Skills: Sec ReportingU.S. GaapWorkiva
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