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Lead the verification efforts for NextSilicon's core product, building a complex verification environment, defining test plans, and ensuring product quality through collaboration with various teams.

Profile and optimize HPC applications across architectures; identify bottlenecks, develop algorithmic and software solutions to accelerate workloads, translate application needs into software/hardware features, and build performance models for future architectures.

Lead porting and performance analysis of diverse HPC applications on novel architectures. Profile node- and scale-level bottlenecks, design algorithmic/software solutions, translate application needs into software and hardware features, and develop performance models for future hardware.

The DFT Engineer will implement DFT methodologies for SOCs, develop tests for verifying DFT functionality, collaborate with cross-functional teams on ASIC products, and solve testing challenges.

Act as primary technical liaison between customers and engineering to support, profile, troubleshoot, and optimize scientific HPC applications across architectures. Reproduce and resolve client-facing bugs, drive feature requests, maintain documentation, and advocate customer needs to product and software teams.

Act as primary technical liaison for HPC customers: troubleshoot and reproduce issues, optimize parallel applications, profile performance across architectures, drive product features through customer engagement, maintain documentation, and advocate customer needs to engineering teams.

Lead porting and performance analysis of HPC applications at node and at scale. Profile bottlenecks, design algorithmic and software optimizations for a novel dataflow architecture, translate application needs into software features and hardware requirements, and build performance models for future architectures.

Provide hands-on technical support for HPC scientific applications, troubleshoot and reproduce client issues, profile and optimize parallel code, and drive product improvements through customer engagement and collaboration with engineering and product teams. Maintain documentation and act as a liaison between customers and internal stakeholders to translate needs into features.

Design and implement virtualization support for RISC-V architecture, ensuring compliance and optimization of the software stack for performance in virtualized workloads.

Manage the complete program lifecycle of hardware development, from architecture to tapeout, ensuring quality, scope, and schedule are met.