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The role involves physical design engineering, leading backend initiatives and working collaboratively on advanced HPC product designs, focusing on critical performance metrics and methodologies.

The role involves developing a runtime compiler for accelerating HPC and AI applications, requiring collaboration with hardware teams and designing APIs for integration.

The engineer will optimize AI libraries and components for unique hardware, focusing on performance improvements in AI models and kernels.

The AI Compiler Engineer will develop the AI graph compiler and work on the software stack to optimize AI models for unique hardware architecture. Responsibilities include enhancing performance for AI models and contributing to related components in the software stack.

Develop a new communication stack, including network drivers and user-space libraries, focused on low-latency applications and collaboration with hardware teams.

Lead physical design projects, collaborating with teams to meet challenges in area, timing, and layout. Ensure robust verification and implementation of methodologies.

Lead the design of advanced RISC-V CPU ASICs, drive execution across teams, and ensure successful tape-out and product bring-up. Requires 6+ years experience in ASIC design.

The Emulation Engineer will develop emulation models for NextSilicon accelerators, optimizing for speed and collaborating with various teams to ensure performance goals are met.

Lead the verification efforts for NextSilicon's core product, building a complex verification environment, defining test plans, and ensuring product quality through collaboration with various teams.

Profile and optimize HPC applications across architectures; identify bottlenecks, develop algorithmic and software solutions to accelerate workloads, translate application needs into software/hardware features, and build performance models for future architectures.