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Act as primary technical liaison for HPC customers: troubleshoot and reproduce issues, optimize parallel applications, profile performance across architectures, drive product features through customer engagement, maintain documentation, and advocate customer needs to engineering teams.

Lead porting and performance analysis of HPC applications at node and at scale. Profile bottlenecks, design algorithmic and software optimizations for a novel dataflow architecture, translate application needs into software features and hardware requirements, and build performance models for future architectures.

Provide hands-on technical support for HPC scientific applications, troubleshoot and reproduce client issues, profile and optimize parallel code, and drive product improvements through customer engagement and collaboration with engineering and product teams. Maintain documentation and act as a liaison between customers and internal stakeholders to translate needs into features.

Design and implement virtualization support for RISC-V architecture, ensuring compliance and optimization of the software stack for performance in virtualized workloads.

Manage the complete program lifecycle of hardware development, from architecture to tapeout, ensuring quality, scope, and schedule are met.

Develop, optimize, and productionize mathematical algorithms for a general-purpose coprocessor. Explore graph theory and clustering approaches, analyze application code and performance data, and collaborate cross-functionally to translate research into practical high-performance computing solutions.

Develop a toolchain and compiler stack for next-generation hardware, focusing on backend development within the LLVM compiler and low-level optimizations.

Develop and optimize compiler analyses and transformations for an adaptive runtime targeting NextSilicon hardware. Contribute to MLIR/LLVM upstream, benchmark HPC applications, identify optimization opportunities, and collaborate with software, HPC application, and hardware teams to improve performance.

Design, implement, test, and maintain high- and low-level compiler optimizations and analyses for HPC applications on custom hardware. Contribute to upstream MLIR/LLVM, benchmark applications, identify optimization opportunities, and collaborate with software, hardware, and application teams to drive runtime compiler performance.

Design, implement, test, and maintain high- and low-level compiler optimizations and analyses for HPC applications on specialized hardware. Contribute to upstream MLIR and LLVM, develop an adaptive runtime compiler, benchmark applications to identify optimization opportunities, and collaborate with software, HPC, and hardware teams.