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Design-for-test (DFT) engineer responsible for DFT structures (scan chains, scan compression), generating and analyzing ATPG coverage, optimizing test coverage, and running gate simulation to verify scan patterns for ASICs.

Design and verify microarchitecture and RTL for high-speed PHYs and datapaths. Perform timing closure, timing constraints, PTSI, DFT insertion, and STA. Build HVL-based testbenches, linting and synthesis flows, and work with high-speed IO blocks (PLLs, DLLs, LDOs). Apply low-power techniques and collaborate across distributed teams.

Plan and execute system tests for Bluetooth, BLE, and wireless charging; perform log analysis and debugging; optimize performance metrics (stability, latency, throughput, audio); run field and interoperability tests; attend industry test events and liaise with standards bodies.