Top Tech Jobs & Startup Jobs

Leads complex Digital IP and subsystem development programs from planning through release and SoC integration readiness. Manages integrated plans, schedules, dependencies, risks, resources, deliverables, and release criteria while coordinating architecture, design, verification, validation, software, and integration teams. Provides executive visibility through technical reviews, dashboards, KPIs, metrics, status updates, risk escalation, and decision management. Supports portfolio planning, resource prioritization, capacity management, and cross-functional execution across multiple product lines.

Provides technical leadership for digital IP verification, including verification planning, UVM testbench development, constrained-random and directed testing, coverage analysis, assertions, formal verification, debugging, and root-cause analysis. Mentors engineers and promotes zero-defect verification practices for automotive and microcontroller semiconductor products.

Own end-to-end physical design implementation for complex SoC and IP blocks from netlist through GDSII. Responsibilities include floorplanning, power planning, placement, CTS, routing, timing closure, PPA optimization, physical verification, IR-drop and electromigration analysis, DRC/LVS closure, ECOs, tapeout support, methodology automation, cross-functional collaboration, design reviews, and mentoring junior engineers.

Leads NXP’s China marketing and communications team, translating business and global priorities into measurable campaigns, brand positioning, executive communications, reputation management, thought leadership, and stakeholder engagement. Builds relationships with media, analysts, influencers, developers, partners, universities, and government stakeholders. Drives AI-enabled digital customer journeys, content, events, and ecosystem engagement across automotive, industrial, and consumer markets while measuring business and communications impact.

Lead physical design implementation and signoff for complex ASIC SoC and IP blocks in advanced technology nodes. Responsibilities include floorplanning, power grid design, placement, optimization, clock tree synthesis, routing, timing closure across MCMM scenarios, DRC/LVS signoff, IR drop and electromigration compliance, congestion and crosstalk debugging, ECO execution, cross-functional collaboration, and scripting-based methodology improvements.

Owns the strategy, development, positioning, and go-to-market execution for a Battery Management Systems semiconductor portfolio. Leads cross-functional collaboration across engineering, sales, applications, and operations; engages customers in market needs, design-ins, quotations, samples, and documentation; and drives product launches and competitive differentiation. Requires strong semiconductor and electrical systems knowledge, stakeholder influence, resilience, and global travel.

Provides expert-level functional safety assessments and peer reviews for safety-related automotive semiconductor software and SoC products. Performs ISO 26262 assessments, safety concept reviews, and safety analyses including FTA, SW FMEA, and DFA. Drives safety software innovation, promotes functional safety culture, aligns technical and business stakeholders, and supports system safety solution development. Domestic and international travel is required.

Performs RTL synthesis and front-end implementation for digital ASIC/SoC designs, optimizing timing, power, and area. Develops SDC constraints, conducts static timing analysis and formal equivalency verification, and supports timing closure. Automates synthesis and analysis flows using Tcl, Python, and Perl. Collaborates with RTL, DFT, and physical design teams, evaluates CAD tools, and documents methodologies and results.

Lead pre-silicon verification of digital IP modules and subsystems. Develop verification plans, UVM environments, test cases, stimulus, assertions, and regression tests. Execute simulations across RTL, power-aware RTL, gate-level, FPGA, and emulation platforms; debug designs and analyze code and functional coverage. Collaborate with hardware, firmware, software, architecture, and systems engineering teams.

Coordinate and govern a portfolio of Data Engineering, DevOps, and Platform Engineering initiatives. Own program strategy, roadmaps, intake, prioritization, delivery governance, financials, resource planning, risk management, stakeholder communication, and executive reporting across multiple teams and projects.