Top Tech Jobs & Startup Jobs

Lead digital verification for PMICs from planning through signoff. Create SystemVerilog/UVM environments, constrained-random tests, SVA/formal checks, coverage-driven regressions, and automation. Verify interfaces, power sequencing, diagnostics, safety, and embedded control. Deliver verification collateral, drive methodology improvements, and mentor junior engineers across global teams.

Design CMOS SRAM and ROM circuits and periphery to meet compiler performance, power, and area targets. Create and run simulation characterization and testbenches, work with layout and CAD teams, ensure frontend model alignment, and collaborate globally to share methodologies and implement GenAI/EDA efficiencies.

Characterize and model next-generation non-volatile memory (NVM) technologies, perform statistical reliability analysis, set qualification requirements, collaborate with foundries and product teams to ensure high-volume production reliability, and communicate results to internal and external stakeholders.

Own assigned products' technical aspects to manage cost and quality. Drive yield, test-time, and CoNQ improvements, support NPI, transfers, ramp-up, root-cause analysis with 8D, and collaborate with business, manufacturing, and factory engineering to ensure manufacturable, high-quality products.

The Senior DFT Engineer will design, implement, and verify DFT architectures for complex SoCs, collaborating with various teams to ensure high-quality silicon and robust testability.

Design and deliver digital functions for wireless/communication ASICs across IP, subsystem, and IC levels. Lead RTL coding, verification, synthesis, timing closure, DFT, backend support, silicon validation and bring-up. Produce design documentation and participate in digital/system problem solving.

Lead pre-silicon verification of IP modules/subsystems: define verification plans, build and run UVM-based testbenches, develop tests/stimulus/assertions, run simulations/emulation, and analyze coverage and regressions.

Design and deliver high-speed, high-linearity analog and SERDES circuit blocks for automotive transceivers, focusing on block-level ownership and silicon validation.

Verify complex digital IPs and subsystems (RISC-V cores, memory controllers, interconnects). Define verification plans, develop UVM-based testbenches, create tests, run regressions across RTL/gate/FPGA/emulation, analyze coverage, and debug pre- and post-silicon issues while collaborating with HW, FW, SW, and architecture teams.

Design and develop reusable digital IPs for SoC integration: create RTL from micro-architecture, optimize for power/performance/area, run lint/CDC/synthesis/STA checks, drive bug closure, support sign-offs, and collaborate with verification and post-silicon teams.