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As a Design Verification Engineer, you will develop verification plans, validate designs, execute test cases, and analyze simulation results to ensure quality in semiconductor designs.

The Hardware Design Architect will drive architecture innovations for Hardware Design, collaborating with various teams to ensure solutions align with business needs and technical specifications.

The Software DevOps Engineer will develop, enhance, and implement software systems for generative AI, focusing on backend development, quality assurance, and scalability.

The Senior DFT Engineer will design, implement, and verify DFT architectures for SoCs, collaborating with various teams to ensure silicon quality and robustness.

The SoC Front End Design Engineer will work on designing and developing SoC architectures, perform RTL design, verification, and collaborate with teams to optimize designs for performance and efficiency.

The Sr. Project Manager will lead a cross-functional team in automotive IC development, ensuring project execution, stakeholder alignment, and adherence to quality standards.

The role involves defining and developing data & AI architecture, guiding innovation, and collaborating with global teams to implement secure AI solutions.

The SoC Architect will define and drive the architecture of next-gen microcontrollers, lead architectural decisions, and collaborate with teams to integrate systems, focusing on real-time, power efficiency, and security.

Provide first-line IT support and monitoring for manufacturing and business systems (Windows/Linux/MES). Troubleshoot end-user computing, business applications, and shopfloor/tester systems; escalate complex issues to regional/global teams. Deliver remote support across sites, document knowledge, and participate in 24x7 rotational shifts to ensure continuous service availability.

Lead development and execution of SoC/IP verification suites using UVM/SystemVerilog and C-based DV. Create tests, run RTL/gate-level/power-aware simulations and emulation, collect coverage, debug design issues, drive DV closure across IPs, improve flows for reuse, and mentor junior engineers while collaborating with design teams for sign-off.