Top Tech Jobs & Startup Jobs

Own end-to-end SoC program execution from definition through tape-out and post-silicon support. Lead technical decisions across architecture, RTL, integration, verification, DFT, emulation, physical design, AMS, IP, and validation teams. Manage cross-functional execution, schedules, resources, dependencies, risks, tape-out readiness, silicon bring-up, and issue resolution. Partner with PMO, product, system, NPI, business, and external stakeholders while communicating progress, risks, and mitigation plans.

Leads verification planning and execution for block, subsystem, and SoC designs. Develops scalable SystemVerilog/UVM testbenches, reusable verification components, constrained-random and directed tests, assertions, coverage models, and formal properties. Drives functional, code, assertion, and toggle coverage closure; debugs simulation failures; and supports sign-off. Verifies interconnects, cache coherency, memory, boot/reset, low-power, performance, and stress scenarios. Provides technical leadership, mentoring, hiring support, and process improvement.

Develop and architect system management firmware for NXP i.MX SoCs and development boards. Responsibilities include porting firmware, integrating with system ROM, U-Boot, ARM Trusted Firmware, Linux, and MCU SDK components, developing tests, measuring performance, documenting solutions, and debugging customer systems. The role requires embedded C development, Linux tooling, ARM Cortex-M/A experience, and ARM assembly knowledge.

Lead complete static timing analysis signoff for SoCs or subsystems through tapeout. Develop and validate timing constraints, collaborate with frontend, DFT, and IP teams, and manage SDF generation and validation. Drive signal integrity closure, apply AI in STA activities, and support physical design problem-solving and strategy across advanced technology nodes. Requires strong knowledge of placement, clock tree synthesis, routing, physical design flows, and signoff leadership.

Defines, designs, verifies, evaluates, and documents digital functions for IPs, subsystems, or ICs according to specifications, quality, and reliability requirements. Participates in resolving digital and system-level device issues and authors design-specific documentation for internal and external audiences.

Designs, verifies, evaluates, and documents digital functions at the IP, subsystem, and IC levels. Ensures designs meet specifications, quality, and reliability requirements while contributing to problem-solving across digital and system domains.

Design and implement AI/ML compiler technologies for embedded ARM and RISC-V hardware using C++ and LLVM. Develop MLIR and graph compiler features, optimize model lowering, fusion, tiling, scheduling, code generation, and inference performance. Collaborate with hardware architects, ML researchers, and global development teams to support automotive system-on-chip platforms. Analyze generated code with simulators and profilers while contributing to open-source compiler technologies.

Develop AI/ML compiler technologies for embedded ARM and RISC-V processors, optimizing models through graph compilation, lowering, fusion, tiling, scheduling, code generation, and performance analysis. The role involves C++ and LLVM/MLIR development, collaboration with hardware architects and ML researchers, compiler support for automotive SoCs, and contribution to open-source projects.

Design and implement AI/ML compiler technologies for embedded ARM and RISC-V processors using C++, LLVM, and MLIR. Optimize machine learning models through graph-level transformations, lowering, fusion, tiling, scheduling, code generation, and performance analysis. Collaborate with hardware architects, ML researchers, compiler consumers, and global development teams to deliver production compiler features for automotive SoCs.

Develop AI/ML compiler technologies for embedded hardware using C++ and LLVM, optimizing models for high-performance inference across semiconductor platforms. Build compiler features for ARM and RISC-V processors, including graph optimizations, model lowering, code generation, and optimization pipelines. Collaborate with architecture teams, internal tool users, and global development teams throughout design, development, and deployment.