Top Tech Jobs & Startup Jobs

Ph.D. interns apply machine learning and AI to semiconductor chip design or enterprise engineering tools. Responsibilities include developing ML models for EDA automation, placement, timing, power, and verification, or deploying LLM, RAG, and agentic systems. Interns will train, evaluate, and deploy models, conduct rigorous experiments, collaborate with engineering and technology stakeholders, assess production performance and safety, and present findings to leadership. The role requires doctoral research in AI, machine learning, computer science, electrical engineering, data science, or a related field.

Ph.D. interns design, simulate, characterize, and validate silicon photonics components, optical engines, and DSP algorithms for PAM4 and coherent optical transceivers. Responsibilities include optical system modeling, link budget analysis, lab testing, silicon bring-up, and collaboration with analog IC, packaging, and systems engineering teams. Interns present research findings and design results while contributing to production-scale optical communications solutions.

Lead transition and sustainment of silicon photonics and optical transceiver products from NPI to volume production. Collaborate with US and CM teams to improve yield, implement in-process controls, manage production risks, and perform failure analysis at chip/SiPho and optical subassembly levels while owning product lifecycle activities.

Lead development and release of wafer-sort and production test programs on ATE and bench platforms. Drive test flow optimization, yield improvement, and test-time reduction. Collaborate with design, product engineering, DFT/DFM, and OSATs to qualify products, manage test inventory, and resolve yield issues for high-speed RF/mixed-signal ICs.

Develop, automate, and maintain optical/electrical test methodologies and stations for silicon photonics products; support NPI and high-volume manufacturing ramps, collaborate cross-functionally, work with vendors/FA teams, and document test procedures and learnings.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K/Teradyne. Design high-speed ATE hardware, create test plans, convert design test patterns to ATE format, optimize test flows, collaborate with DFx/design, and ensure DFT/MBIST and high-speed interface compliance.

Lead development of ATE test solutions for characterization, wafer sort, and production on Advantest 93K/Teradyne UltraFLEX. Design high-speed test hardware, define test methodologies, translate simulation patterns to ATE programs, optimize test flows, and collaborate cross-functionally to improve yield and release production test programs.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest/Teradyne platforms. Design high-speed ATE hardware, define test methodologies, translate simulation patterns to production test programs, optimize test flows, and collaborate with product, hardware, design, and firmware teams to improve yield and test efficiency.

Develops high-speed IC packages from concept through tapeout, including C4 and BGA ball maps, netlist mappings, die placement, padstacks, connectivity, and package requirement documents. Collaborates with architecture, chip, board, manufacturing, and simulation teams to optimize signal and power integrity, manufacturability, reliability, thermal performance, and cost. Supports advanced packaging architectures, design-flow development, library maintenance, and scripting automation.

Lead development of ATE test solutions and hardware on Advantest/Teradyne platforms; create test plans; convert design patterns to ATE; collaborate with DFx and design teams; optimize test flows to improve yields and reduce test time; release production test programs and support wafer sort and characterization.