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Develop and maintain automated QA and validation tests for PCIe, CXL, DDR, memory controller, storage, and firmware products. Create Python and C/C++ unit and integration tests using Pytest and GTest, debug automation failures, analyze firmware logs and protocol traces, and integrate testing into CI/CD pipelines. Collaborate cross-functionally on protocol compliance, performance validation, and high-quality releases.

Develops and executes quality assurance strategies for Marvell switch platforms, SDKs, NOS solutions, firmware, and embedded systems. Responsibilities include test planning, functional and performance testing, Python automation, CI/CD integration, coverage improvement, packet and protocol validation, defect reporting, and release qualification. The role requires troubleshooting low-level networking and firmware behavior, reviewing test results, participating in code reviews, and collaborating across development, validation, and release teams.

Design, develop, and maintain production-grade QA and automation systems for C/C++ and Python components. Create and enhance Pytest and GTest test suites, debug failures using language-specific tools, validate firmware and CXL/PCIe technologies, and integrate testing into CI/CD pipelines. The role contributes to architecture, code reviews, technical decisions, cross-functional planning, and mentoring while applying AI tools and prompt engineering to improve test generation and quality.

Lead semiconductor product engineering activities for server and network processors, including ATE test development, product characterization, yield optimization, test-flow improvement, and production qualification. Collaborate with design, hardware, firmware, DFT/DFM, process, and test teams to resolve yield, quality, test-time, and customer issues. Support wafer sort, final test, SLT, RMA analysis, package and fab qualifications, and new-product launches.

Ph.D. interns apply machine learning and AI to semiconductor chip design or enterprise engineering tools. Responsibilities include developing ML models for EDA automation, placement, timing, power, and verification, or deploying LLM, RAG, and agentic systems. Interns will train, evaluate, and deploy models, conduct rigorous experiments, collaborate with engineering and technology stakeholders, assess production performance and safety, and present findings to leadership. The role requires doctoral research in AI, machine learning, computer science, electrical engineering, data science, or a related field.

Ph.D. interns design, simulate, characterize, and validate silicon photonics components, optical engines, and DSP algorithms for PAM4 and coherent optical transceivers. Responsibilities include optical system modeling, link budget analysis, lab testing, silicon bring-up, and collaboration with analog IC, packaging, and systems engineering teams. Interns present research findings and design results while contributing to production-scale optical communications solutions.

Lead transition and sustainment of silicon photonics and optical transceiver products from NPI to volume production. Collaborate with US and CM teams to improve yield, implement in-process controls, manage production risks, and perform failure analysis at chip/SiPho and optical subassembly levels while owning product lifecycle activities.

Lead development and release of wafer-sort and production test programs on ATE and bench platforms. Drive test flow optimization, yield improvement, and test-time reduction. Collaborate with design, product engineering, DFT/DFM, and OSATs to qualify products, manage test inventory, and resolve yield issues for high-speed RF/mixed-signal ICs.

Develop, automate, and maintain optical/electrical test methodologies and stations for silicon photonics products; support NPI and high-volume manufacturing ramps, collaborate cross-functionally, work with vendors/FA teams, and document test procedures and learnings.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K/Teradyne. Design high-speed ATE hardware, create test plans, convert design test patterns to ATE format, optimize test flows, collaborate with DFx/design, and ensure DFT/MBIST and high-speed interface compliance.