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Design highly sophisticated CMOS transceiver/SERDES products, implement and verify circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs to meet performance targets using industry standard tools.

Take responsibility for projects, performing end-to-end SI/PI analysis on high-speed traces and critical power domains to ensure performance meets specifications. Own all steps in supporting SI/PI including modeling, simulation, measurement, and customer support. Collaborate with packaging and board layout teams to define specifications and provide feedback for improvements.

Develop and maintain verification environment using Verilog, System Verilog, and UVM. Define and review verification test plans, verify design with functional parameters, maintain regression tests, analyze verification coverage, and drive verification to reach targets.

Lead the design verification of complex CPU sub-systems, mentor and guide a team of design verification engineers, own the sub-system verification flows, methodologies, and verification of IP/Sub-system.

Join Marvell as a Senior Staff RTL Design Engineer working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.

Contribute to high-speed and high-performance SerDes development in advanced technology nodes. Design IP and provide instructions to layout engineers. Support IP characterization, validation, lab characterization, and customer support. Requires 5+ years of experience in high speed analog mixed signal design in 5nm and below for TSMC process.

Senior Principal Engineer role at Marvell focusing on FW design, implementation, qualification, and customer support within an SoC development organization. Requires 8 years of experience with strong software/firmware engineering background and knowledge of C, C++, Python.