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The Senior Layout PCB Engineer will design and optimize PCBs for high-speed applications, focusing on signaling, power distribution, and complex HDI stack-ups, while collaborating with teams to enhance performance and manufacturability.

Build critical infrastructure and custom applications, collaborate cross-functionally, and address operational challenges with a strong focus on delivering production-level code rapidly.

Work with package, PCB, ASIC, and system engineers to analyze high-speed interfaces (PCIe, Ethernet, SerDes), extract and validate S-parameter models, build HFSS 3D EM models, correlate simulation with lab measurements, and recommend design improvements to improve signal and power integrity across accelerator platforms.

Lead formal verification for complex ASIC IP and SoC subsystems. Define strategy, write SVA properties, build reusable formal environments, drive proof convergence, debug RTL/protocol bugs with formal counterexamples, and collaborate with architects, RTL, UVM DV, emulation, software, and firmware teams toward formal sign-off.

Design, develop, and test simulations for custom hardware systems, ensuring accuracy and performance while collaborating with hardware and software teams.

The Head of Lab Operations will manage lab operations, oversee team supervision, coordinate hardware validation, and maintain lab infrastructure.

The Physical Design Engineer will focus on block-level implementation, timing closure, PPA optimization, and supervising outsourced design work while improving design flows.

The Technical Program Manager will oversee program delivery, align teams, manage vendor relationships, and optimize processes in the Infrastructure organization.

Lead the global contract manufacturing strategy for advanced AI hardware systems, managing relationships with partners and ensuring production efficiency.

As a Design Verification Engineer, you will create and maintain UVM/SystemVerilog testbenches, execute verification plans, debug issues, and collaborate with cross-functional teams to ensure IP functionality and performance.