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Build and embed LLM-agent workflows into silicon engineering flows (RTL, verification, DFT, physical design, validation). Integrate agents with simulators, regressions, lab equipment, and CI; design rigorous evals, drive adoption, and accelerate chip development through measurable automation.

The Talent Intern will handle scheduling, logistics of interviews, manage candidate communications, support operational recruiting tasks, and improve the candidate experience while collaborating with recruitment teams.

Intern will develop firmware for ASICs, focusing on hardware reliability, performance, and collaboration with cross-functional teams to support AI applications.

As a Physical Design intern, you will assist in silicon design, improve iteration speed, develop design flows, and conduct final design checks.

Lead the full-cycle recruiting process for technical talent, partner with hiring managers, and enhance candidate experience in a high-paced environment.

The RTL Design Engineer will develop design verification strategies for ASIC designs, ensuring efficiency and performance of AI chips.

The Product Quality Engineer oversees quality assurance and inspection processes, collaborates with teams, drives improvements, and resolves manufacturing issues for AI hardware.

The Design Verification Engineer will ensure all architecture requirements are met by collaborating with vendors and internal teams, developing verification environments, and validating external IPs within chip architecture.

Develop cutting-edge software for AI inference systems, solving challenges across software stacks and contributing to innovative AI solutions.

The Design Verification Engineer will verify performance features in ASIC designs, collaborate with teams, and enhance performance models.