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Own end-to-end product economics across semiconductor and system costs, manufacturing, supply, inventory, pricing, customer monetization, and margins. Build financial models, product-roadmap business cases, forecasts, dashboards, and investment analyses. Partner with Product, Engineering, Manufacturing, Supply Chain, GTM, and Finance to improve margins, guide capital allocation, and translate AI infrastructure performance into pricing and executive decisions.

Research and write technically rigorous content about AI, inference, compute, chips, systems, and infrastructure. Responsibilities include long-form analysis, product launches, leadership ghostwriting, customer case studies, technical briefs, social content, and data-driven visuals. The role partners closely with engineers and executives to develop original viewpoints, explain complex concepts, and establish Etched’s technical voice across audiences and channels.

Own and architect the automated RTL-to-GDSII physical design flow: build/maintain CAD infrastructure, automate regressions and run management, integrate signoff tools, create PG meshes and DRC-clean floorplans, drive PPA tuning and timing correlation, and partner with block owners to encode methodology fixes for scalable tapeout.

Own block- and subsystem-level physical design from synthesis through GDSII sign-off: floorplanning, synthesis, placement, CTS, routing, timing closure, signoff (EM/IR/RC/DRC/LVS), generate abstracts and timing budgets, collaborate with RTL designers, and supervise outsourced PD work.

Lead full-chip physical implementation from synthesis to GDSII: floorplanning, P&R, clocking, MMMC timing closure, timing constraints and ECOs, full-chip physical verification (DRC/LVS/ERC/antenna/density/fill), debug PV violations, and tapeout signoff using automated flows and Innovus.

Lead end-to-end manufacturing test program management from prototype through mass production. Define test strategy, coordinate cross-functional teams, deploy test hardware/software/fixtures with CM/FATP partners, drive yield improvements and failure analysis, and travel to manufacturing sites to ensure production readiness.

Lead schematic and board development for accelerator systems, collaborate with SI/PCB/mechanical teams and ODMs/OEMs, manage PCBA documentation and BOMs, perform bring-up and validation, define test plans and manufacturing test equipment, and ensure datacenter requirements for high-power AI servers are met.

Own demand forecasting, supply planning, and finished-goods inventory to meet S&OP objectives. Build and execute weekly, monthly, and quarterly demand-supply plans; monitor planned vs. actual builds and inventory across SKUs; translate forecasts into executable build plans with Manufacturing and Global Supply Management; lead scenario planning and risk mitigation under capacity or component constraints; and drive continuous improvement of planning processes, tools, and models.

The Quality Engineer will oversee quality assurance processes for suppliers and integrators of advanced AI hardware, ensuring compliance with standards and driving continuous improvement.

Manage corporate governance, board processes, financings, transaction closings, entity and equity administration, contract lifecycle tasks, and maintain legal records and workflows to support a rapidly scaling hardware and AI infrastructure company.