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8 Hours Ago
Cupertino, CA, USA
53 Employees
Mid level
53 Employees
Mid level
Artificial Intelligence • Hardware • Software
As a Procurement professional at Etched, you will manage vendor relationships, expedite purchasing processes, and ensure timely materials delivery for production. You'll create systems for tracking orders, negotiate contracts, and evaluate suppliers to optimize the procurement function.
8 Hours Ago
Cupertino, CA, USA
53 Employees
Mid level
53 Employees
Mid level
Artificial Intelligence • Hardware • Software
The Principal Design Verification Engineer will develop ASIC testbenches, implement micro-architecture using System Verilog, and collaborate with design teams to ensure microchip functionality. Responsibilities include executing functional verification, applying timing closure methods, utilizing formal verification tools, debugging designs, and documenting the verification process.
8 Hours Ago
Cupertino, CA, USA
53 Employees
Junior
53 Employees
Junior
Artificial Intelligence • Hardware • Software
The Physical Design Engineer will manage outsourcing for physical design, verify designs, and improve iteration speed. Responsibilities include overseeing design flows, optimizing tool usage, and facilitating block-level closure while collaborating with EDA vendors and supporting the ASIC infrastructure.
8 Hours Ago
Cupertino, CA, USA
53 Employees
Senior level
53 Employees
Senior level
Artificial Intelligence • Hardware • Software
The Firmware Engineer will design, implement, and optimize firmware for AI accelerator systems, conduct debugging and validation in various environments, and collaborate with hardware engineers to enhance performance. Key responsibilities include firmware development for RTOS embedded systems and proposing improvements for future AI accelerator generations.
16 Days Ago
Cupertino, CA, USA
53 Employees
Senior level
53 Employees
Senior level
Artificial Intelligence • Hardware • Software
The Principal Physical Design Engineer at Etched will oversee 3rd party design services, optimize physical design tool flows, and drive project convergence dashboards while ensuring backend design and timing closure. The role requires experience in low power design methodologies and familiarity with automated RTL-to-GDSII flows.
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