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Designs complex IC substrate packages for high-power AI processors and accelerators. Responsibilities include large multi-layer substrate layouts, power delivery networks exceeding 700W, high-speed signaling above 50GHz, CoWoS interposer optimization, SI/PI collaboration, DRC and LVS verification, manufacturability support, documentation, design reviews, and technical guidance for junior engineers.

Support People Operations and Legal through compliance audits, employee records review, filings, contracts, onboarding and offboarding, recruiting handoffs, process documentation, and cross-functional company projects. The intern will investigate discrepancies, organize sensitive information, research requirements, coordinate across teams, and drive time-sensitive operational work to completion in a fully in-person San Jose office.

Build and deploy production-level solutions for Etched’s critical engineering challenges. Projects may include internal hardware tools, manufacturing execution systems, or agentic AI systems for R&D. The intern will own a project from scoping through production, working across full-stack engineering, infrastructure, and product development in a fast-paced, ambiguous environment.

Designs complex IC substrate packages for high-power AI processors and accelerators, including large multilayer layouts, dense routing, power delivery networks, and signaling beyond 50GHz. The role optimizes CoWoS interposer designs, performs DRC and LVS verification, collaborates with silicon, SI/PI, packaging, and manufacturing teams, and supports design reviews and technical guidance for junior engineers.

Manage and maintain Allegro schematic symbol and PCB footprint libraries. Create, validate, and organize accurate, manufacturable ECAD components; maintain metadata, part numbering, approvals, and datasheet links. Collaborate with electrical, layout, manufacturing, and supplier teams to resolve library issues, meet IPC, JEDEC, and DFM requirements, and improve fabrication yield. Perform quality checks and use version control and SKILL scripting to preserve data integrity and automate library tasks.

Coordinates inbound and outbound international shipments from pickup through delivery, maintaining accurate ERP and inventory records. Monitors transit times, delivery performance, costs, and exceptions; works with freight forwarders, customs brokers, warehouses, suppliers, and contract manufacturers to resolve issues. Reviews shipping documentation, supports inventory control, builds recurring logistics reports, and improves SOPs and processes. The role requires knowledge of Taiwan import/export operations, international freight, Incoterms, and professional English and Mandarin proficiency.

Own block- and subsystem-level physical design from RTL synthesis through GDSII sign-off. Perform floorplanning, placement, CTS, routing, timing closure, sign-off (EM/IR/RC/DRC/LVS), generate abstracts for hierarchical integration, improve PPA with RTL collaboration, and supervise third-party delivery.

Lead external financial reporting and equity accounting, including stock-based compensation, EPS/dilution, SEC filings (10-Q/10-K), XBRL tagging, auditor coordination, SOX controls, and selection/implementation of reporting systems to build scalable reporting infrastructure.

Design and validate power delivery networks for high-current ASIC systems: perform PDN pre/post-layout analysis, DC IR-drop and AC impedance simulations, VRM modeling, thermal co-simulation, DRC/PI checks, bring-up debug, and maintain simulation-to-hardware correlation.

The Physical Design Engineer will focus on block-level implementation, timing closure, PPA optimization, and supervising outsourced design work while improving design flows.