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The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

Lead the verification of Serdes systems, develop UVM/SV testbenches and test cases, and mentor junior engineers while ensuring design quality and integration.

As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.