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Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.

The Principal Digital Verification Engineer will lead technical verification of chiplet products, develop UVM-based test environments, execute verification plans, and mentor junior engineers.

Lead STA signoff processes for complex ASIC designs, defining methodologies and collaborating with design teams to ensure timing closure and optimal performance.

As a Principal Physical Design Engineer, you will lead ASIC development from RTL to GDSII, oversee design flow optimization, and ensure the delivery of high-performance products.

The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.

As a Verification Engineer, you will lead the verification of Serdes by developing AMS SystemVerilog models, collaborating with the design team, and ensuring model quality.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

Lead ASIC and platform development, manage cross-functional teams, oversee project timelines, budgets, and vendor relationships to ensure successful program delivery.

The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.

Lead and scale a design verification team for PHY and controller products. Define verification strategy and methodology (UVM, AMS, formal), drive verification planning and execution across link layer, PCS, PMA, and FEC, integrate analog models into digital flows, manage tapeout verification milestones, improve verification infrastructure and CI/CD, ensure standards compliance, and oversee vendor VIPs and firmware co-simulation for tapeout readiness.