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Design and optimize hardware interfaces, collaborate with ML and hardware teams, and ensure software and hardware integration.

Lead integrated NPI lifecycle for rack- and board-level AI systems, coordinating CM/JDM partners, PLM/BOM/ECO control, factory test deployment, quality and yield metrics, and high-volume ramp readiness while reporting risks and readiness to executives.

Develop and sign-off performant silicon from RTL to GDSII across blocks, subsystems, and full-chip. Lead partitioning, floorplanning, synthesis, P&R, clocking, verification, timing/power sign-off, and collaborate with Design, Verification, and DFT teams to meet tapeout milestones.

Design and implement compilers for proprietary hardware architecture, focusing on midend and backend development, while providing hardware insights.

The Architect will oversee hardware architecture, collaborate with teams, and enhance silicon design performance for AI models.

Develop and execute Rust tests to verify silicon designs and software, ensuring they conform to specifications by identifying discrepancies before production.

Lead the design of next-generation AI-focused silicon by translating product requirements into SoC architectures and collaborating with teams on power and performance trade-offs.

Develop and maintain performance models of hardware, while collaborating with architecture and runtime teams. Optimize performance and contribute to architectural reviews.

As a SOC Integration Engineer, you will develop and integrate SOC RTL designs, collaborate with cross-functional teams, and ensure high-quality silicon integration.

Lead the design and architecture of AI-focused SoC systems, defining specifications, driving power-performance-area trade-offs, and collaborating with cross-functional teams on system integration.